Commit c8d2d725 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Modified Xilinx Benchmark Table for Xilinx.

parent 02285c0e
Pipeline #5336 passed with stages
in 10 minutes
......@@ -20564,7 +20564,7 @@ BRAMs
\begin_inset Text
\begin_layout Plain Layout
2 500
2640
\end_layout
\end_inset
......@@ -20573,7 +20573,7 @@ BRAMs
\begin_inset Text
\begin_layout Plain Layout
1 569
1489
\end_layout
\end_inset
......@@ -20620,7 +20620,7 @@ BRAMs
\begin_inset Text
\begin_layout Plain Layout
2 661
2741
\end_layout
\end_inset
......@@ -20629,7 +20629,7 @@ BRAMs
\begin_inset Text
\begin_layout Plain Layout
1 714
1625
\end_layout
\end_inset
......@@ -20676,7 +20676,7 @@ BRAMs
\begin_inset Text
\begin_layout Plain Layout
2 819
2834
\end_layout
\end_inset
......@@ -20685,7 +20685,7 @@ BRAMs
\begin_inset Text
\begin_layout Plain Layout
1 867
1770
\end_layout
\end_inset
......@@ -20732,7 +20732,7 @@ BRAMs
\begin_inset Text
\begin_layout Plain Layout
3 030
3106
\end_layout
\end_inset
......@@ -20741,7 +20741,7 @@ BRAMs
\begin_inset Text
\begin_layout Plain Layout
1 942
1905
\end_layout
\end_inset
......@@ -20788,7 +20788,7 @@ BRAMs
\begin_inset Text
\begin_layout Plain Layout
3 177
3157
\end_layout
\end_inset
......@@ -20797,7 +20797,7 @@ BRAMs
\begin_inset Text
\begin_layout Plain Layout
2 004
1908
\end_layout
\end_inset
......
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