Commit c858a760 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '339-fix-psl-coverage' into 'master'

Resolve "Fix PSL coverage"

Closes #339

See merge request !298
parents b911b68d 9cc67c0c
Pipeline #13673 passed with stage
in 17 seconds
Subproject commit 8da042c5123ae4b566f3270686eadb15d144eba7
Subproject commit ca7524b99d6d43b49a15428d6f9c6aeca6c59437
......@@ -1238,38 +1238,38 @@ begin
-- Transmitted frame combinations (no RTR)
-- psl tx_base_id_can_2_0_cov : cover
-- (tran_ident_type = BASE and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '0');
-- {tran_ident_type = BASE and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '0'};
-- psl tx_extended_id_can_2_0_cov : cover
-- (tran_ident_type = EXTENDED and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '0');
-- {tran_ident_type = EXTENDED and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '0'};
-- psl tx_base_id_can_fd_cov : cover
-- (tran_ident_type = BASE and tran_frame_type = FD_CAN and
-- tran_is_rtr = '0');
-- {tran_ident_type = BASE and tran_frame_type = FD_CAN and
-- tran_is_rtr = '0'};
-- psl tx_extended_id_can_fd_cov : cover
-- (tran_ident_type = EXTENDED and tran_frame_type = FD_CAN and
-- tran_is_rtr = '0');
-- {tran_ident_type = EXTENDED and tran_frame_type = FD_CAN and
-- tran_is_rtr = '0'};
-- RTR frames (in combination with FD_CAN, this is ignored!)
-- psl tx_base_id_can_2_0_rtr_cov : cover
-- (tran_ident_type = BASE and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '1');
-- {tran_ident_type = BASE and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '1'};
-- psl tx_extended_id_can_2_0_rtr_cov : cover
-- (tran_ident_type = EXTENDED and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '1');
-- {tran_ident_type = EXTENDED and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '1'};
-- psl tx_base_id_can_fd_rtr_cov : cover
-- (tran_ident_type = BASE and tran_frame_type = FD_CAN and
-- tran_is_rtr = '1');
-- {tran_ident_type = BASE and tran_frame_type = FD_CAN and
-- tran_is_rtr = '1'};
-- psl tx_extended_id_can_fd_rtr_cov : cover
-- (tran_ident_type = EXTENDED and tran_frame_type = FD_CAN and
-- tran_is_rtr = '1');
-- {tran_ident_type = EXTENDED and tran_frame_type = FD_CAN and
-- tran_is_rtr = '1'};
-- <RELEASE_ON>
......
......@@ -2967,88 +2967,88 @@ begin
-- Error frame request in various parts of CAN frame!
-- psl err_frm_req_in_sof_cov : cover
-- (curr_state = s_pc_sof and err_frm_req);
-- {curr_state = s_pc_sof and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_base_id_in_base_cov : cover
-- (curr_state = s_pc_base_id and err_frm_req);
-- {curr_state = s_pc_base_id and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ext_id_in_ext_id_cov : cover
-- (curr_state = s_pc_ext_id and err_frm_req);
-- {curr_state = s_pc_ext_id and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ext_id_in_rtr_srr_r1_cov : cover
-- (curr_state = s_pc_rtr_srr_r1 and err_frm_req);
-- {curr_state = s_pc_rtr_srr_r1 and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ext_id_in_ide_cov : cover
-- (curr_state = s_pc_ide and err_frm_req);
-- {curr_state = s_pc_ide and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_rtr_r1_cov : cover
-- (curr_state = s_pc_rtr_r1 and err_frm_req);
-- {curr_state = s_pc_rtr_r1 and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_edl_r1_cov : cover
-- (curr_state = s_pc_edl_r1 and err_frm_req);
-- {curr_state = s_pc_edl_r1 and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_r0_ext_cov : cover
-- (curr_state = s_pc_r0_ext and err_frm_req);
-- {curr_state = s_pc_r0_ext and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_r0_fd_cov : cover
-- (curr_state = s_pc_r0_fd and err_frm_req);
-- {curr_state = s_pc_r0_fd and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_edl_r0_cov : cover
-- (curr_state = s_pc_edl_r0 and err_frm_req);
-- {curr_state = s_pc_edl_r0 and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_esi_cov : cover
-- (curr_state = s_pc_esi and err_frm_req);
-- {curr_state = s_pc_esi and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_dlc_cov : cover
-- (curr_state = s_pc_dlc and err_frm_req);
-- {curr_state = s_pc_dlc and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_data_cov : cover
-- (curr_state = s_pc_data and err_frm_req);
-- {curr_state = s_pc_data and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_stuff_count_cov : cover
-- (curr_state = s_pc_stuff_count and err_frm_req);
-- {curr_state = s_pc_stuff_count and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_crc_cov : cover
-- (curr_state = s_pc_crc and err_frm_req);
-- {curr_state = s_pc_crc and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_crc_delim_cov : cover
-- (curr_state = s_pc_crc_delim and err_frm_req);
-- {curr_state = s_pc_crc_delim and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ack_cov : cover
-- (curr_state = s_pc_ack and err_frm_req);
-- {curr_state = s_pc_ack and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_eof_cov : cover
-- (curr_state = s_pc_eof and err_frm_req);
-- {curr_state = s_pc_eof and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_act_err_flag_cov : cover
-- (curr_state = s_pc_act_err_flag and err_frm_req);
-- {curr_state = s_pc_act_err_flag and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_pas_err_flag_cov : cover
-- (curr_state = s_pc_pas_err_flag and err_frm_req);
-- {curr_state = s_pc_pas_err_flag and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ovr_flag_cov : cover
-- (curr_state = s_pc_ovr_flag and err_frm_req);
-- {curr_state = s_pc_ovr_flag and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ovr_delim_cov : cover
-- (curr_state = s_pc_ovr_delim and err_frm_req);
-- {curr_state = s_pc_ovr_delim and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_err_delim_cov : cover
-- (curr_state = s_pc_err_delim and err_frm_req);
-- {curr_state = s_pc_err_delim and err_frm_req = '1'};
-- Overload frame requests
-- psl ovr_from_eof_cov : cover
-- (curr_state = s_pc_eof and next_state = s_pc_ovr_flag);
-- {curr_state = s_pc_eof and next_state = s_pc_ovr_flag};
-- psl ovr_from_intermission_cov : cover
-- (curr_state = s_pc_intermission and next_state = s_pc_ovr_flag);
-- {curr_state = s_pc_intermission and next_state = s_pc_ovr_flag};
-- psl ovr_from_err_delim : cover
-- (curr_state = s_pc_err_delim and next_state = s_pc_ovr_flag);
-- {curr_state = s_pc_err_delim and next_state = s_pc_ovr_flag};
-- psl ovr_from_ovr_delim_cov : cover
-- (curr_state = s_pc_ovr_delim and next_state = s_pc_ovr_flag);
-- {curr_state = s_pc_ovr_delim and next_state = s_pc_ovr_flag};
-- <RELEASE_ON>
......
......@@ -300,84 +300,84 @@ begin
-- {int_vect_i(RXI_IND) = '0';int_vect_i(RXI_IND) = '1'};
-- psl rxi_enable_cov : cover
-- (int_vect_i(RXI_IND) = '1' and int_ena(RXI_IND) = '1');
-- {int_vect_i(RXI_IND) = '1' and int_ena(RXI_IND) = '1'};
-- psl txi_set_cov : cover
-- {int_vect_i(TXI_IND) = '0';int_vect_i(TXI_IND) = '1'};
-- psl txi_enable_cov : cover
-- (int_vect_i(TXI_IND) = '1' and int_ena(TXI_IND) = '1');
-- {int_vect_i(TXI_IND) = '1' and int_ena(TXI_IND) = '1'};
-- psl ewli_int_set_cov : cover
-- {int_vect_i(EWLI_IND) = '0';int_vect_i(EWLI_IND) = '1'};
-- psl ewli_enable_cov : cover
-- (int_vect_i(EWLI_IND) = '1' and int_ena(EWLI_IND) = '1');
-- {int_vect_i(EWLI_IND) = '1' and int_ena(EWLI_IND) = '1'};
-- psl doi_int_set_cov : cover
-- {int_vect_i(DOI_IND) = '0';int_vect_i(DOI_IND) = '1'};
-- psl doi_enable_cov : cover
-- (int_vect_i(DOI_IND) = '1' and int_ena(DOI_IND) = '1');
-- {int_vect_i(DOI_IND) = '1' and int_ena(DOI_IND) = '1'};
-- psl fcsi_int_set_cov : cover
-- {int_vect_i(FCSI_IND) = '0';int_vect_i(FCSI_IND) = '1'};
-- psl fcsi_enable_cov : cover
-- (int_vect_i(FCSI_IND) = '1' and int_ena(FCSI_IND) = '1');
-- {int_vect_i(FCSI_IND) = '1' and int_ena(FCSI_IND) = '1'};
-- psl ali_int_set_cov : cover
-- {int_vect_i(ALI_IND) = '0';int_vect_i(ALI_IND) = '1'};
-- psl ali_enable_cov : cover
-- (int_vect_i(ALI_IND) = '1' and int_ena(ALI_IND) = '1');
-- {int_vect_i(ALI_IND) = '1' and int_ena(ALI_IND) = '1'};
-- psl beu_int_set_cov : cover
-- {int_vect_i(BEI_IND) = '0';int_vect_i(BEI_IND) = '1'};
-- psl bei_enable_cov : cover
-- (int_vect_i(BEI_IND) = '1' and int_ena(BEI_IND) = '1');
-- {int_vect_i(BEI_IND) = '1' and int_ena(BEI_IND) = '1'};
-- psl rxfi_int_set_cov : cover
-- {int_vect_i(RXFI_IND) = '0';int_vect_i(RXFI_IND) = '1'};
-- psl rxfi_enable_cov : cover
-- (int_vect_i(RXFI_IND) = '1' and int_ena(RXFI_IND) = '1');
-- {int_vect_i(RXFI_IND) = '1' and int_ena(RXFI_IND) = '1'};
-- psl bsi_int_set_cov : cover
-- {int_vect_i(BSI_IND) = '0';int_vect_i(BSI_IND) = '1'};
-- psl bsi_enable_cov : cover
-- (int_vect_i(BSI_IND) = '1' and int_ena(BSI_IND) = '1');
-- {int_vect_i(BSI_IND) = '1' and int_ena(BSI_IND) = '1'};
-- psl rbnei_int_set_cov : cover
-- {int_vect_i(RBNEI_IND) = '0';int_vect_i(RBNEI_IND) = '1'};
-- psl rbnei_enable_cov : cover
-- (int_vect_i(RBNEI_IND) = '1' and int_ena(RBNEI_IND) = '1');
-- {int_vect_i(RBNEI_IND) = '1' and int_ena(RBNEI_IND) = '1'};
-- psl txbhci_int_set_cov : cover
-- {int_vect_i(TXBHCI_IND) = '0';int_vect_i(TXBHCI_IND) = '1'};
-- psl txbhci_enable_cov : cover
-- (int_vect_i(TXBHCI_IND) = '1' and int_ena(TXBHCI_IND) = '1');
-- {int_vect_i(TXBHCI_IND) = '1' and int_ena(TXBHCI_IND) = '1'};
-- psl ofi_int_set_cov : cover
-- {int_vect_i(OFI_IND) = '0';int_vect_i(OFI_IND) = '1'};
-- psl ofi_enable_cov : cover
-- (int_vect_i(OFI_IND) = '1' and int_ena(OFI_IND) = '1');
-- {int_vect_i(OFI_IND) = '1' and int_ena(OFI_IND) = '1'};
-- <RELEASE_ON>
end architecture;
\ No newline at end of file
......@@ -901,46 +901,46 @@ begin
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- psl rx_buf_empty_cov :
-- cover (rx_empty = '1');
-- cover {rx_empty = '1'};
--
-- psl rx_buf_not_empty_to_empty_cov :
-- cover {rx_empty = '0'; rx_empty = '1'};
--
-- psl rx_buf_rx_full_cov :
-- cover (rx_full = '1');
-- cover {rx_full = '1'};
--
-- psl rx_buf_rx_full_to_not_full_cov :
-- cover {(rx_full = '1'); (rx_full = '0')};
--
-- psl rx_buf_overrun_cov :
-- cover (overrun_condition = '1');
-- cover {overrun_condition = '1'};
--
-- psl rx_buf_commit_overrun_abort_cov :
-- cover (commit_overrun_abort = '1');
-- cover {commit_overrun_abort = '1'};
--
-- psl rx_buf_overrun_flags_cov :
-- cover (data_overrun_i = '1' and data_overrun_flg = '1');
-- cover {data_overrun_i = '1' and data_overrun_flg = '1'};
--
-- psl rx_buf_overrun_clear_cov :
-- cover (drv_clr_ovr = '1');
-- cover {drv_clr_ovr = '1'};
--
-- psl rx_buf_write_ts_cov :
-- cover (write_ts = '1');
-- cover {write_ts = '1'};
--
-- psl rx_buf_release_receive_buffer_cov :
-- cover (drv_erase_rx = '1');
-- cover {drv_erase_rx = '1'};
--
-- psl rx_buf_commit_and_read_cov :
-- cover (read_increment = '1' and commit_rx_frame = '1');
-- cover {read_increment = '1' and commit_rx_frame = '1'};
--
-- psl rx_buf_commit_after_read_cov :
-- cover {read_increment = '1'; commit_rx_frame = '1'};
-- cover {read_increment = '1'; commit_rx_frame = '1'};
--
-- psl rx_buf_read_after_commit_cov :
-- cover {commit_rx_frame = '1'; read_increment = '1'};
--
-- psl rx_buf_write_and_read_cov :
-- cover (write_raw_intent = '1' and read_increment = '1');
-- cover {write_raw_intent = '1' and read_increment = '1'};
--
-- psl rx_buf_read_after_write_cov :
-- cover {write_raw_intent = '1'; read_increment = '1'};
......@@ -949,10 +949,10 @@ begin
-- cover {read_increment = '1'; write_raw_intent = '1'};
--
-- psl rx_buf_sof_timestamp :
-- cover (drv_rtsopt = RTS_BEG and commit_rx_frame = '1');
-- cover {drv_rtsopt = RTS_BEG and commit_rx_frame = '1'};
--
-- psl rx_buf_eof_timestamp :
-- cover (drv_rtsopt = RTS_END and commit_rx_frame = '1');
-- cover {drv_rtsopt = RTS_END and commit_rx_frame = '1'};
--
-- psl rx_buf_burst_read_short_cov :
-- cover {(read_increment = '1')[*4]};
......@@ -961,34 +961,34 @@ begin
-- cover {(read_increment = '1')[*20]};
--
-- psl rx_buf_frame_abort_cov :
-- cover (rec_abort_f = '1');
-- cover {rec_abort_f = '1'};
--
-- psl rx_buf_store_rtr_cov :
-- cover (rec_is_rtr = '1' and commit_rx_frame = '1');
-- cover {rec_is_rtr = '1' and commit_rx_frame = '1'};
--
-- psl rx_buf_store_empty_frame_cov :
-- cover (rec_dlc = "0000" and rec_is_rtr = '0' and commit_rx_frame = '1');
-- cover {rec_dlc = "0000" and rec_is_rtr = '0' and commit_rx_frame = '1'};
--
-- psl rx_buf_store_1_byte_frame_cov :
-- cover (rec_dlc = "0001" and rec_is_rtr = '0' and commit_rx_frame = '1');
-- cover {rec_dlc = "0001" and rec_is_rtr = '0' and commit_rx_frame = '1'};
--
-- psl rx_buf_store_2_byte_frame_cov :
-- cover (rec_dlc = "0010" and rec_is_rtr = '0' and commit_rx_frame = '1');
-- cover {rec_dlc = "0010" and rec_is_rtr = '0' and commit_rx_frame = '1'};
--
-- psl rx_buf_store_3_byte_frame_cov :
-- cover (rec_dlc = "0011" and rec_is_rtr = '0' and commit_rx_frame = '1');
-- cover {rec_dlc = "0011" and rec_is_rtr = '0' and commit_rx_frame = '1'};
--
-- psl rx_buf_store_4_byte_frame_cov :
-- cover (rec_dlc = "0100" and rec_is_rtr = '0' and commit_rx_frame = '1');
-- cover {rec_dlc = "0100" and rec_is_rtr = '0' and commit_rx_frame = '1'};
--
-- psl rx_buf_store_5_byte_frame_cov :
-- cover (rec_dlc = "0101" and rec_is_rtr = '0' and commit_rx_frame = '1');
-- cover {rec_dlc = "0101" and rec_is_rtr = '0' and commit_rx_frame = '1'};
--
-- psl rx_buf_store_8_byte_frame_cov :
-- cover (rec_dlc = "1000" and rec_is_rtr = '0' and commit_rx_frame = '1');
-- cover {rec_dlc = "1000" and rec_is_rtr = '0' and commit_rx_frame = '1'};
--
-- psl rx_buf_store_64_byte_frame_cov :
-- cover (rec_dlc = "1111" and rec_is_rtr = '0' and commit_rx_frame = '1');
-- cover {rec_dlc = "1111" and rec_is_rtr = '0' and commit_rx_frame = '1'};
-- <RELEASE_ON>
......
......@@ -393,22 +393,22 @@ begin
-- psl default clock is rising_edge(clk_sys);
--
-- psl rx_no_raw_mem_free_cov :
-- cover (to_integer(unsigned(rx_mem_free_raw)) = 0);
-- cover {to_integer(unsigned(rx_mem_free_raw)) = 0};
--
-- psl rx_all_raw_mem_free_cov :
-- cover (to_integer(unsigned(rx_mem_free_raw)) = G_RX_BUFF_SIZE);
-- cover {to_integer(unsigned(rx_mem_free_raw)) = G_RX_BUFF_SIZE};
--
-- psl rx_no_int_mem_free_cov :
-- cover (to_integer(unsigned(rx_mem_free_i)) = 0);
-- cover {to_integer(unsigned(rx_mem_free_i)) = 0};
--
-- psl rx_all_int_mem_free_cov :
-- cover (to_integer(unsigned(rx_mem_free_i)) = G_RX_BUFF_SIZE);
-- cover {to_integer(unsigned(rx_mem_free_i)) = G_RX_BUFF_SIZE};
--
-- psl rx_write_ptr_higher_than_read_ptr_cov :
-- cover (write_pointer_i > read_pointer_i);
-- cover {write_pointer_i > read_pointer_i};
--
-- psl rx_read_ptr_higher_than_write_ptr_cov :
-- cover (read_pointer_i > write_pointer_i);
-- cover {read_pointer_i > write_pointer_i};
-- <RELEASE_ON>
end architecture;
\ No newline at end of file
......@@ -579,22 +579,22 @@ begin
-- psl default clock is rising_edge(clk_sys);
-- psl txt_lock_cov : cover
-- (txtb_hw_cmd.lock = '1');
-- {txtb_hw_cmd.lock = '1'};
--
-- psl txt_unlock_cov : cover
-- (txtb_hw_cmd.unlock = '1');
-- {txtb_hw_cmd.unlock = '1'};
--
-- psl txt_lock_buf_1_cov : cover
-- (txtb_hw_cmd_index = 0 and txtb_hw_cmd.lock = '1');
-- {txtb_hw_cmd_index = 0 and txtb_hw_cmd.lock = '1'};
--
-- psl txt_lock_buf_2_cov : cover
-- (txtb_hw_cmd_index = 1 and txtb_hw_cmd.lock = '1');
-- {txtb_hw_cmd_index = 1 and txtb_hw_cmd.lock = '1'};
--
-- psl txt_lock_buf_3_cov : cover
-- (txtb_hw_cmd_index = 2 and txtb_hw_cmd.lock = '1');
-- {txtb_hw_cmd_index = 2 and txtb_hw_cmd.lock = '1'};
--
-- psl txt_lock_buf_4_cov : cover
-- (txtb_hw_cmd_index = 3 and txtb_hw_cmd.lock = '1');
-- {txtb_hw_cmd_index = 3 and txtb_hw_cmd.lock = '1'};
--
-- psl txt_prio_change_cov : cover
-- {select_buf_avail = '1';
......@@ -605,8 +605,8 @@ begin
-- same priority are available! Here we only test the proper index selection
-- in case of equal priorities!
-- psl txt_buf_eq_priority_cov : cover
-- (txtb_available(0) = '1' and txtb_available(1) = '1' and
-- txtb_prorities(0) = txtb_prorities(1))
-- {txtb_available(0) = '1' and txtb_available(1) = '1' and
-- txtb_prorities(0) = txtb_prorities(1)}
-- report "Selected Buffer index changed while buffer selected";
--
-- Change of buffer from available to not available but not due to lock
......@@ -617,15 +617,15 @@ begin
-- report "Buffer became non-ready but not due to lock command";
--
-- psl txt_buf_all_available_cov : cover
-- (txtb_available(0) = '1' and txtb_available(1) = '1' and
-- txtb_available(2) = '1' and txtb_available(3) = '1');
-- {txtb_available(0) = '1' and txtb_available(1) = '1' and
-- txtb_available(2) = '1' and txtb_available(3) = '1'};
--
-- psl txt_buf_change_cov : cover
-- (txtb_changed = '1' and txtb_hw_cmd.lock = '1')
-- {txtb_changed = '1' and txtb_hw_cmd.lock = '1'}
-- report "TX Buffer changed between two frames";
--
-- psl txt_buf_sim_chng_and_lock_cov : cover
-- (select_index_changed = '1' and txtb_hw_cmd.lock = '1');
-- {select_index_changed = '1' and txtb_hw_cmd.lock = '1'};
----------------------------------------------------------------------------
-- Functional coverage for Priority decoder!
......@@ -636,42 +636,42 @@ begin
-- Combinations in first comparator!
-- psl prio_dec_stage_1_cov_1 : cover
-- ((unsigned(txtb_prorities(0)) > unsigned(txtb_prorities(1))) and
-- txtb_available(0) = '1' and txtb_available(1) = '1');
-- {(unsigned(txtb_prorities(0)) > unsigned(txtb_prorities(1))) and
-- txtb_available(0) = '1' and txtb_available(1) = '1'};
-- psl prio_dec_stage_1_cov_2 : cover
-- ((unsigned(txtb_prorities(0)) < unsigned(txtb_prorities(1))) and
-- txtb_available(0) = '1' and txtb_available(1) = '1');
-- {(unsigned(txtb_prorities(0)) < unsigned(txtb_prorities(1))) and
-- txtb_available(0) = '1' and txtb_available(1) = '1'};
-- psl prio_dec_stage_1_cov_3 : cover
-- ((unsigned(txtb_prorities(0)) = unsigned(txtb_prorities(1))) and
-- txtb_available(0) = '1' and txtb_available(1) = '1');
-- {(unsigned(txtb_prorities(0)) = unsigned(txtb_prorities(1))) and
-- txtb_available(0) = '1' and txtb_available(1) = '1'};
-- psl prio_dec_stage_1_cov_4 : cover
-- (txtb_available(0) = '0' and txtb_available(1) = '1');
-- {txtb_available(0) = '0' and txtb_available(1) = '1'};
-- psl prio_dec_stage_1_cov_5 : cover
-- (txtb_available(0) = '1' and txtb_available(1) = '0');
-- {txtb_available(0) = '1' and txtb_available(1) = '0'};
-- Combinations in second comparator!
-- psl prio_dec_stage_2_cov_1 : cover
-- ((unsigned(txtb_prorities(2)) > unsigned(txtb_prorities(3))) and
-- txtb_available(2) = '1' and txtb_available(3) = '1');
-- {(unsigned(txtb_prorities(2)) > unsigned(txtb_prorities(3))) and
-- txtb_available(2) = '1' and txtb_available(3) = '1'};
-- psl prio_dec_stage_2_cov_2 : cover
-- ((unsigned(txtb_prorities(2)) < unsigned(txtb_prorities(3))) and
-- txtb_available(2) = '1' and txtb_available(3) = '1');
-- {(unsigned(txtb_prorities(2)) < unsigned(txtb_prorities(3))) and
-- txtb_available(2) = '1' and txtb_available(3) = '1'};
-- psl prio_dec_stage_2_cov_3 : cover
-- ((unsigned(txtb_prorities(2)) = unsigned(txtb_prorities(3))) and
-- txtb_available(2) = '1' and txtb_available(3) = '1');
-- {(unsigned(txtb_prorities(2)) = unsigned(txtb_prorities(3))) and
-- txtb_available(2) = '1' and txtb_available(3) = '1'};
-- psl prio_dec_stage_2_cov_4 : cover
-- (txtb_available(2) = '0' and txtb_available(3) = '1');
-- {txtb_available(2) = '0' and txtb_available(3) = '1'};
-- psl prio_dec_stage_2_cov_5 : cover
-- (txtb_available(2) = '1' and txtb_available(3) = '0');
-- {txtb_available(2) = '1' and txtb_available(3) = '0'};
-----------------------------------------------------------------------------
......
......@@ -455,62 +455,62 @@ begin
-- LOCK commands in various parts of TXT Buffer validation
-- psl txtb_lock_arb_sel_low_cov : cover
-- (curr_state = s_arb_sel_low_ts and txtb_hw_cmd.lock = '1');
-- {curr_state = s_arb_sel_low_ts and txtb_hw_cmd.lock = '1'};
--
-- psl txtb_lock_arb_sel_hi_cov : cover
-- (curr_state = s_arb_sel_upp_ts and txtb_hw_cmd.lock = '1');
-- {curr_state = s_arb_sel_upp_ts and txtb_hw_cmd.lock = '1'};
--
-- psl txtb_lock_arb_sel_ffw_cov : cover
-- (curr_state = s_arb_sel_ffw and txtb_hw_cmd.lock = '1');
-- {curr_state = s_arb_sel_ffw and txtb_hw_cmd.lock = '1'};
--
-- psl txtb_lock_arb_sel_idw_cov : cover
-- (curr_state = s_arb_sel_idw and txtb_hw_cmd.lock = '1');
-- {curr_state = s_arb_sel_idw and txtb_hw_cmd.lock = '1'};
--
-- psl txtb_lock_arb_sel_validated_cov : cover
-- (curr_state = s_arb_validated and txtb_hw_cmd.lock = '1');
-- {curr_state = s_arb_validated and txtb_hw_cmd.lock = '1'};
-- TXT Buffer becoming suddenly unavailable during TXT Buffer validation
-- psl_txtb_not_available_arb_sel_low_cov : cover
-- (curr_state = s_arb_sel_low_ts and select_buf_avail = '0');
-- {curr_state = s_arb_sel_low_ts and select_buf_avail = '0'};
--
-- psl_txtb_not_available_arb_sel_upp_cov : cover
-- (curr_state = s_arb_sel_upp_ts and select_buf_avail = '0');
-- {curr_state = s_arb_sel_upp_ts and select_buf_avail = '0'};
--
-- psl_txtb_not_available_arb_sel_ffw_cov : cover
-- (curr_state = s_arb_sel_ffw and select_buf_avail = '0');
-- {curr_state = s_arb_sel_ffw and select_buf_avail = '0'};
--
-- psl_txtb_not_available_arb_sel_idw_cov : cover
-- (curr_state = s_arb_sel_idw and select_buf_avail = '0');
-- {curr_state = s_arb_sel_idw and select_buf_avail = '0'};
--
-- psl_txtb_not_available_arb_validated_cov : cover
-- (curr_state = s_arb_validated and select_buf_avail = '0');
-- {curr_state = s_arb_validated and select_buf_avail = '0'};
-- TXT Buffer index change during TXT Buffer validation
-- psl_txtb_changed_arb_sel_low_cov : cover
-- (curr_state = s_arb_sel_low_ts and select_index_changed = '0');
-- {curr_state = s_arb_sel_low_ts and select_index_changed = '0'};
--
-- psl_txtb_changed_arb_sel_upp_cov : cover
-- (curr_state = s_arb_sel_upp_ts and select_index_changed = '0');
-- {curr_state = s_arb_sel_upp_ts and select_index_changed = '0'};
--
-- psl_txtb_changed_arb_sel_ffw_cov : cover
-- (curr_state = s_arb_sel_ffw and select_index_changed = '0');
-- {curr_state = s_arb_sel_ffw and select_index_changed = '0'};
--
-- psl_txtb_changed_arb_sel_idw_cov : cover
-- (curr_state = s_arb_sel_idw and select_index_changed = '0');
-- {curr_state = s_arb_sel_idw and select_index_changed = '0'};
--
-- psl_txtb_changed_arb_validated_cov : cover
-- (curr_state = s_arb_validated and select_index_changed = '0');
-- {curr_state = s_arb_validated and select_index_changed = '0'};
-- Waiting till timestamp will be ready (transmission at given time)
-- psl txt_buf_wait_till_timestamp_cov : cover
-- (curr_state = s_arb_sel_upp_ts and fsm_wait_state_q = '0' and
-- timestamp_valid = '0');
-- {curr_state = s_arb_sel_upp_ts and fsm_wait_state_q = '0' and
-- timestamp_valid = '0'};
------------------------------------------------------------------------------
-- Assertions
......
......@@ -270,17 +270,17 @@ begin
-- psl default clock is rising_edge(clk_sys);
-- Each SW command active
-- psl txtb_set_ready_cov : cover (txtb_sw_cmd.set_rdy = '1' and sw_cbs = '1');
-- psl txtb_set_empty_cov : cover (txtb_sw_cmd.set_ety = '1' and sw_cbs = '1');
-- psl txtb_set_abort_cov : cover (txtb_sw_cmd.set_abt = '1' and sw_cbs = '1');
-- psl txtb_set_ready_cov : cover {txtb_sw_cmd.set_rdy = '1' and sw_cbs = '1'};
-- psl txtb_set_empty_cov : cover {txtb_sw_cmd.set_ety = '1' and sw_cbs = '1'};
-- psl txtb_set_abort_cov : cover {txtb_sw_cmd.set_abt = '1' and sw_cbs = '1'};
-- HW Commands
-- psl txtb_hw_lock : cover (txtb_hw_cmd.lock = '1' and hw_cbs = '1');
-- psl txtb_hw_unlock : cover (txtb_hw_cmd.unlock = '1' and hw_cbs = '1');
-- psl txtb_hw_valid : cover (txtb_hw_cmd.valid = '1' and hw_cbs = '1');
-- psl txtb_hw_err : cover (txtb_hw_cmd.err = '1' and hw_cbs = '1');
-- psl txtb_hw_arbl : cover (txtb_hw_cmd.arbl = '1' and hw_cbs = '1');
-- psl txtb_hw_failed : cover (txtb_hw_cmd.failed = '1' and hw_cbs = '1');
-- psl txtb_hw_lock : cover {txtb_hw_cmd.lock = '1' and hw_cbs = '1'};
-- psl txtb_hw_unlock : cover {txtb_hw_cmd.unlock = '1' and hw_cbs = '1'};
-- psl txtb_hw_valid : cover {txtb_hw_cmd.valid = '1' and hw_cbs = '1'};
-- psl txtb_hw_err : cover {txtb_hw_cmd.err = '1' and hw_cbs = '1'};
-- psl txtb_hw_arbl : cover {txtb_hw_cmd.arbl = '1' and hw_cbs = '1'};
-- psl txtb_hw_failed : cover {txtb_hw_cmd.failed = '1' and hw_cbs = '1'};
end block;
......
......@@ -370,23 +370,23 @@ begin
-- psl default clock is rising_edge(clk_sys);
-- Each FSM state
-- psl txtb_fsm_empty_cov : cover (curr_state = s_txt_empty);
-- psl txtb_fsm_ready_cov : cover (curr_state = s_txt_ready);
-- psl txtb_fsm_tx_prog_cov : cover (curr_state = s_txt_tx_prog);
-- psl txtb_fsm_ab_prog_cov : cover (curr_state = s_txt_ab_prog);
-- psl txtb_fsm_error_cov : cover (curr_state = s_txt_failed);
-- psl txtb_fsm_aborted_cov : cover (curr_state = s_txt_aborted);