Commit c828d666 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Changed definition of memory blocks. Prefix is now not

included.
parent 6647278c
......@@ -38,8 +38,8 @@
#ifndef __CTU_CAN_FD__
#define __CTU_CAN_FD__
/* CAN_FD_8bit_regs memory map */
enum can_fd_8bit_regs {
/* Regs memory map */
enum regs {
DEVICE_ID = 0x0,
VERSION = 0x2,
MODE = 0x4,
......
# To generate register map package with register addresses and bit offset:
py gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --fieldMap CAN_FD_8bit_regs --addrMap CAN_FD_8bit_regs --wordWidth 32 --outFile ../src/Libraries/CAN_FD_register_map.vhd --packName CAN_FD_register_map
py gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --fieldMap Regs --addrMap Regs --wordWidth 32 --outFile ../src/Libraries/CAN_FD_register_map.vhd --packName CAN_FD_register_map
# To generate frame format related constants
py gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --fieldMap CAN_FD_frame_format --addrMap CAN_FD_frame_format --wordWidth 32 --outFile ../src/Libraries/CAN_FD_frame_format.vhd --packName CAN_FD_frame_format
py gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --fieldMap Frame_format --addrMap Frame_format --wordWidth 32 --outFile ../src/Libraries/CAN_FD_frame_format.vhd --packName CAN_FD_frame_format
# To generate C header file
py gen_c_header.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap CAN_FD_8bit_regs --fieldMap CAN_FD_8bit_regs --wordWidth 32 --outFile ../driver/kernel_header_draft.h --headName CAN_FD_frame_format
py gen_c_header.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/kernel_header_draft.h --headName CAN_FD_frame_format
# To generate lyx docu for register map
py gen_lyx_docu.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap CAN_FD_8bit_regs --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/registerMap.lyx --chaptName "Register map" --genRegions True --genFiDesc True
# To generate Lyx docu for register map
py gen_lyx_docu.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap Regs --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/registerMap.lyx --chaptName "Register map" --genRegions True --genFiDesc True
# To generate lyx docu for CAN frame
py gen_lyx_docu.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap CAN_FD_frame_format --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/CANFrameFormat.lyx --chaptName "CAN Frame format" --genRegions False --genFiDesc True
# To generate Lyx docu for CAN frame
py gen_lyx_docu.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap Frame_format --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/CANFrameFormat.lyx --chaptName "CAN Frame format" --genRegions False --genFiDesc True
#########################################
......
......@@ -62,19 +62,19 @@ if __name__ == '__main__':
if (str_arg_to_bool(args.updVHDL)):
print("Generating CAN FD memory registers VHDL package...\n")
os.system("""py gen_vhdl_package.py --licPath ../LICENSE --xactSpec {} --fieldMap CAN_FD_8bit_regs --addrMap CAN_FD_8bit_regs --wordWidth 32 --outFile ../src/Libraries/CAN_FD_register_map.vhd --packName CAN_FD_register_map""".format(args.xactSpec))
os.system("""py gen_vhdl_package.py --licPath ../LICENSE --xactSpec {} --fieldMap CAN_FD_frame_format --addrMap CAN_FD_frame_format --wordWidth 32 --outFile ../src/Libraries/CAN_FD_frame_format.vhd --packName CAN_FD_frame_format""".format(args.xactSpec))
os.system("""py gen_vhdl_package.py --licPath ../LICENSE --xactSpec {} --fieldMap Regs --addrMap Regs --wordWidth 32 --outFile ../src/Libraries/CAN_FD_register_map.vhd --packName CAN_FD_register_map""".format(args.xactSpec))
os.system("""py gen_vhdl_package.py --licPath ../LICENSE --xactSpec {} --fieldMap Frame_format --addrMap Frame_format --wordWidth 32 --outFile ../src/Libraries/CAN_FD_frame_format.vhd --packName CAN_FD_frame_format""".format(args.xactSpec))
print("\nDone\n")
if (str_arg_to_bool(args.updHeader)):
print("Generating CAN FD memory registers Header file...\n")
os.system("""py gen_c_header.py --licPath ../LICENSE --xactSpec {} --addrMap CAN_FD_8bit_regs --fieldMap CAN_FD_8bit_regs --wordWidth 32 --outFile ../driver/kernel_header_draft.h --headName CAN_FD_frame_format""".format(args.xactSpec))
os.system("""py gen_c_header.py --licPath ../LICENSE --xactSpec {} --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/kernel_header_draft.h --headName CAN_FD_frame_format""".format(args.xactSpec))
print("\nDone\n")
if (str_arg_to_bool(args.updDocs)):
print("Generating CAN FD memory registers Documentation...\n")
os.system("""py gen_lyx_docu.py --xactSpec {} --memMap CAN_FD_8bit_regs --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/registerMap.lyx --chaptName "Register map" --genRegions True --genFiDesc True""".format(args.xactSpec))
os.system("""py gen_lyx_docu.py --xactSpec {} --memMap CAN_FD_frame_format --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/CANFrameFormat.lyx --chaptName "CAN Frame format" --genRegions False --genFiDesc True""".format(args.xactSpec))
os.system("""py gen_lyx_docu.py --xactSpec {} --memMap Regs --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/registerMap.lyx --chaptName "Register map" --genRegions True --genFiDesc True""".format(args.xactSpec))
os.system("""py gen_lyx_docu.py --xactSpec {} --memMap Frame_format --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/CANFrameFormat.lyx --chaptName "CAN Frame format" --genRegions False --genFiDesc True""".format(args.xactSpec))
print("\nDone\n")
print( 80 * "*")
......
......@@ -6,7 +6,7 @@
<ipxact:version>2.1</ipxact:version>
<ipxact:memoryMaps>
<ipxact:memoryMap>
<ipxact:name>CAN_FD_8bit_regs</ipxact:name>
<ipxact:name>Regs</ipxact:name>
<ipxact:displayName>3. CAN FD Core memory map</ipxact:displayName>
<ipxact:description>CTU CAN FD IP Core is designed as 32 bit peripheria with byte enable support for 8, 16 or 32 bit access. Unaligned access is not supported. Byte or half word access is executed via byte enable signal. The memory is organized as Big endian. Write to read only memory location will have no effect. Read from write only memory location will return zeroes. The memory map consists of following memory regions:</ipxact:description>
<ipxact:addressBlock>
......@@ -3488,7 +3488,7 @@ and synchronisation edge appeared during resynchronisation.</ipxact:description>
<ipxact:addressUnitBits>8</ipxact:addressUnitBits>
</ipxact:memoryMap>
<ipxact:memoryMap>
<ipxact:name>CAN_FD_frame_format</ipxact:name>
<ipxact:name>Frame_format</ipxact:name>
<ipxact:displayName>4. CAN FD frame format</ipxact:displayName>
<ipxact:description>CAN Frame format describtion in as it is stored in TXT Buffers and RX Buffer.</ipxact:description>
<ipxact:addressBlock>
......
......@@ -34,8 +34,8 @@
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Addresses map for: CAN_FD_frame_format
-- Field map for: CAN_FD_frame_format
-- Addresses map for: Frame_format
-- Field map for: Frame_format
-- This file is autogenerated, DO NOT EDIT!
--------------------------------------------------------------------------------
......
......@@ -34,8 +34,8 @@
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Addresses map for: CAN_FD_8bit_regs
-- Field map for: CAN_FD_8bit_regs
-- Addresses map for: Regs
-- Field map for: Regs
-- This file is autogenerated, DO NOT EDIT!
--------------------------------------------------------------------------------
......
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