Commit c6fa2b74 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Relaxed timing conditions in TX Arbitrator Unit test.

Allowed one clock cycle mismatch. On more than one clock cycle,
error is reported.
parent f2bd8951
...@@ -43,6 +43,8 @@ ...@@ -43,6 +43,8 @@
-- 30.5.2016 Created file -- 30.5.2016 Created file
-- 23.4.2018 Updated test to cover TX Arbitrator with continous timestamp -- 23.4.2018 Updated test to cover TX Arbitrator with continous timestamp
-- load. -- load.
-- 5.9.2018 Relaxed timing conditions. Allowed one clock cycle mismatch
-- between DUT and model.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Library ieee; Library ieee;
...@@ -140,6 +142,13 @@ architecture tx_arb_unit_test of CAN_test is ...@@ -140,6 +142,13 @@ architecture tx_arb_unit_test of CAN_test is
-- Delay propagation of metadata to the output! -- Delay propagation of metadata to the output!
signal del_counter : natural; signal del_counter : natural;
-- Signals indicating mismatch between Model and DUT
signal frame_valid_mism : boolean;
signal metadata_mism : boolean;
signal hw_cmd_buf_index_mism : boolean;
signal sel_buf_mism : boolean;
signal mism_ctr : boolean;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Compare function for two 64 bit std logic vectors -- Compare function for two 64 bit std logic vectors
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
...@@ -531,38 +540,46 @@ begin ...@@ -531,38 +540,46 @@ begin
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Compare DUT outputs with model outputs -- Compare DUT outputs with model outputs
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
cmp_proc : process frame_valid_mism <= true when (mod_frame_valid_out /= tran_frame_valid_out and
begin now /= 0 fs)
else
false;
metadata_mism <= true when
(mod_dlc_out /= tran_dlc_out) or
(mod_is_rtr /= tran_is_rtr) or
(mod_ident_type_out /= tran_ident_type_out) or
(mod_frame_type_out /= tran_frame_type_out)) and
now /= 0 fs)
else
false;
hw_cmd_buf_index_mism <= true when (txt_hw_cmd_buf_index /= mod_buf_index and now /= 0 fs)
else
false;
if (mod_frame_valid_out /= tran_frame_valid_out and now /= 0 fs) then sel_buf_mism <= true when (last_locked_index /= mod_buf_index and
-- LCOV_EXCL_START txtb_changed = '0' and now /= 0 fs)
log("DUT and Model Frame valid not matching!", error_l, log_level); else
cmp_err_ctr <= cmp_err_ctr + 1; false;
-- LCOV_EXCL_STOP
end if;
if (((mod_dlc_out /= tran_dlc_out) or
(mod_is_rtr /= tran_is_rtr) or
(mod_ident_type_out /= tran_ident_type_out) or
(mod_frame_type_out /= tran_frame_type_out)) and now /= 0 fs)
then
-- LCOV_EXCL_START
log("DUT and Model metadata not matching!", error_l, log_level);
cmp_err_ctr <= cmp_err_ctr + 1;
-- LCOV_EXCL_STOP
end if;
if (txt_hw_cmd_buf_index /= mod_buf_index and now /= 0 fs) ----------------------------------------------------------------------------
-- Allow only one clock cycle mismatch!
----------------------------------------------------------------------------
cons_check_proc : process
begin
if (frame_valid_mism or metadata_valid_mism or sel_buf_mism or
hw_cmd_buf_index_mism)
then then
-- LCOV_EXCL_START mism_ctr <= mism_ctr + 1;
log("DUT and Model buffer index not matching!", error_l, log_level); else
cmp_err_ctr <= cmp_err_ctr + 1; mism_ctr <= '0';
-- LCOV_EXCL_STOP
end if; end if;
if (last_locked_index /= mod_buf_index and wait for 0 ns;
txtb_changed = '0' and now /= 0 fs)
then if (mism_ctr = 2) then
-- LCOV_EXCL_START -- LCOV_EXCL_START
log("Buffer change not detected!", error_l, log_level); log("Buffer change not detected!", error_l, log_level);
cmp_err_ctr <= cmp_err_ctr + 1; cmp_err_ctr <= cmp_err_ctr + 1;
......
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