Commit c638e462 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch 'rx_data_to_ram' into 'master'

Rx data to ram

See merge request illeondr/CAN_FD_IP_Core!2
parents 1f77dc66 9a8ae5cf
......@@ -2197,7 +2197,7 @@ name "fig:CAN-Core-block"
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="34" columns="5">
<lyxtabular version="3" rows="35" columns="5">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="0pt">
<column alignment="center" valignment="top">
......@@ -3240,7 +3240,7 @@ Acknowledge for TXT Buffers, frame is stored
\begin_inset Text
\begin_layout Plain Layout
rec_data
rec_dram_word
\end_layout
\end_inset
......@@ -3249,7 +3249,7 @@ rec_data
\begin_inset Text
\begin_layout Plain Layout
512
32
\end_layout
\end_inset
......@@ -3276,7 +3276,54 @@ std_logic_vector
\begin_inset Text
\begin_layout Plain Layout
Recieved data
Recieved data on the output of internal RAM
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
rec_dram_addr
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
in
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
natural
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Address pointer for internal RAM
\end_layout
\end_inset
......@@ -16839,7 +16886,7 @@ rec_message_valid
input signal is in logic 1 first word is stored.
In following up to 19 clock cycles remaining words are stored.
This requires the received data to be valid for at least 20 clock cycles
(register in CAN Core).
(RAM in CAN Core).
Since frame is validated at the end of EOF field, until received data are
erased by the next frame, bus is in the intermission field.
Having minimum 7 clock cycles per nominal bit time this gives minimum 21
......@@ -16911,7 +16958,7 @@ rec_message_valid
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="26" columns="5">
<lyxtabular version="3" rows="27" columns="5">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="0pt">
<column alignment="center" valignment="top">
......@@ -17378,7 +17425,7 @@ Recieved identifier
\begin_inset Text
\begin_layout Plain Layout
rec_data_in
rec_dram_word
\end_layout
\end_inset
......@@ -17387,7 +17434,7 @@ rec_data_in
\begin_inset Text
\begin_layout Plain Layout
512
32
\end_layout
\end_inset
......@@ -17396,7 +17443,7 @@ rec_data_in
\begin_inset Text
\begin_layout Plain Layout
in
\end_layout
\end_inset
......@@ -17414,7 +17461,54 @@ std_logic_vector
\begin_inset Text
\begin_layout Plain Layout
Recieved data
Recieved data from Protocol control RAM
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
rec_dram_addr
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
out
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
natural
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Address pointer for Protocol control RAM
\end_layout
\end_inset
......@@ -1934,7 +1934,8 @@ res_n
\series bold
at least two clock cycles
\series default
must elapse before the core is accessed.
must elapse before the core is accessed, otherwise write to the Core will
have no effect and read will return zero values.
The design is intended to be latch-free.
\end_layout
......@@ -2196,7 +2197,7 @@ name "fig:CAN-Core-block"
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="34" columns="5">
<lyxtabular version="3" rows="35" columns="5">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="0pt">
<column alignment="center" valignment="top">
......@@ -3239,7 +3240,7 @@ Acknowledge for TXT Buffers, frame is stored
\begin_inset Text
\begin_layout Plain Layout
rec_data
rec_dram_word
\end_layout
\end_inset
......@@ -3248,7 +3249,7 @@ rec_data
\begin_inset Text
\begin_layout Plain Layout
512
32
\end_layout
\end_inset
......@@ -3275,7 +3276,54 @@ std_logic_vector
\begin_inset Text
\begin_layout Plain Layout
Recieved data
Recieved data on the output of internal RAM
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
rec_dram_addr
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
in
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
natural
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Address pointer for internal RAM
\end_layout
\end_inset
......@@ -16910,7 +16958,7 @@ rec_message_valid
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="26" columns="5">
<lyxtabular version="3" rows="27" columns="5">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="0pt">
<column alignment="center" valignment="top">
......@@ -17377,7 +17425,7 @@ Recieved identifier
\begin_inset Text
\begin_layout Plain Layout
rec_data_in
rec_dram_word
\end_layout
\end_inset
......@@ -17386,7 +17434,7 @@ rec_data_in
\begin_inset Text
\begin_layout Plain Layout
512
32
\end_layout
\end_inset
......@@ -17395,7 +17443,7 @@ rec_data_in
\begin_inset Text
\begin_layout Plain Layout
in
\end_layout
\end_inset
......@@ -17413,7 +17461,54 @@ std_logic_vector
\begin_inset Text
\begin_layout Plain Layout
Recieved data
Recieved data from Protocol control RAM
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
rec_dram_addr
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
out
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
natural
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Address pointer for Protocol control RAM
\end_layout
\end_inset
......@@ -53,6 +53,9 @@ use work.CANconstants.all;
-- Now memory registers set drv_read_start only for ONE clock cycle per each access. So it is enough to
-- check whether signal is active! Thisway it is not necessary to add empty clock cycles between consecutive
-- reads from RX_DATA register!
-- 29.11.2017 Changed hadnling of received data. "rec_data_in" replaced by "rec_dram_word" and "rec_dram_addr" as part of
-- resource optimizations. Data are not available in parallel at input of the RX buffer but addressed in
-- internal RAM of Protocol controller.
--
-----------------------------------------------------------------------------------------------------------------------------------------------------
......@@ -87,7 +90,6 @@ entity rxBuffer is
--CAN Core interface (rec. data,validity, acknowledge)-
-------------------------------------------------------
signal rec_ident_in :in std_logic_vector(28 downto 0); --Message Identifier
signal rec_data_in :in std_logic_vector(511 downto 0); --Message Data (up to 64 bytes);
signal rec_dlc_in :in std_logic_vector(3 downto 0); --Data length code
signal rec_ident_type_in :in std_logic; --Recieved identifier type (0-BASE Format, 1-Extended Format);
signal rec_frame_type_in :in std_logic; --Recieved frame type (0-Normal CAN, 1- CAN FD)
......@@ -98,6 +100,10 @@ entity rxBuffer is
signal rec_message_ack :out std_logic; --Acknowledge for CAN Core about accepted data
signal rec_message_valid :in std_logic; --Output from acceptance filters (out_ident_valid) if message fits the filters
--Added interface for aux SRAM
signal rec_dram_word :in std_logic_vector(31 downto 0);
signal rec_dram_addr :out natural range 0 to 15;
------------------------------------
--Status signals of recieve buffer--
------------------------------------
......@@ -174,13 +180,16 @@ begin
rx_read_buff <= memory(read_pointer) when (memory_valid(read_pointer)='1')
else (OTHERS => '0'); --Read data from SRAM memory (1 port, async read)
-- Address for the Receive data RAM in the CAN Core!
-- Comparator is temporary before the data order will be reversed!
rec_dram_addr <= 18-copy_counter when (copy_counter>2 and copy_counter<19) else 0;
------------------------------------------------------------------
--Storing data from CANCore and loading data into reading buffer--
------------------------------------------------------------------
memory_acess:process(clk_sys,res_n)
variable data_length : natural range 0 to 16; --Length variable for frame stored into reading buffer (in 32 bit words)
variable mem_free : natural range 0 to buff_size; --Amount of free words
variable mem_free : natural range 0 to buff_size:= buff_size; --Amount of free words
variable message_count : natural range 0 to 255; --Message Count already stored
begin
if (res_n=ACT_RESET) or (drv_erase_rx='1') then
......@@ -354,8 +363,9 @@ begin
elsif(copy_counter<data_size)then -- Here the data words are stored
--Note: copy_counter is at least 3 here!! (3 to 18), therefore we have to decrease it by 3 -> increase the index by 96
memory(write_pointer) <= rec_data_in(607-((copy_counter)*32) downto 576-((copy_counter)*32));
--Optimized implementation of the storing with auxiliarly receive data RAM
memory(write_pointer) <= rec_dram_word;
memory_valid(write_pointer) <= '1';
write_pointer <= (write_pointer+1) mod buff_size;
copy_counter <= copy_counter+1;
......
......@@ -91,7 +91,6 @@ entity core_top is
--Recieve Buffer and Message Filter Interface--
-----------------------------------------------
signal rec_ident_out :out std_logic_vector(28 downto 0); --Message Identifier
signal rec_data_out :out std_logic_vector(511 downto 0); --Message Data (up to 64 bytes);
signal rec_dlc_out :out std_logic_vector(3 downto 0); --Data length code
signal rec_ident_type_out :out std_logic; --Recieved identifier type (0-BASE Format, 1-Extended Format);
signal rec_frame_type_out :out std_logic; --Recieved frame type (0-Normal CAN, 1- CAN FD)
......@@ -100,6 +99,8 @@ entity core_top is
signal rec_esi_out :out std_logic; --Error state indicator
signal rec_message_valid_out :out std_logic; --Output from acceptance filters (out_ident_valid) if message fits the filters
signal rec_message_ack_out :in std_logic; --Acknowledge for CAN Core about accepted data
signal rec_dram_word_out :out std_logic_vector(31 downto 0);
signal rec_dram_addr_out :in natural range 0 to 15;
-------------------------------
--Interrupt Manager Interface--
......@@ -264,7 +265,6 @@ entity core_top is
signal dec_one : std_logic;
--Protocol control signals
signal rec_data : std_logic_vector(511 downto 0);
signal rec_ident : std_logic_vector(28 downto 0);
signal rec_dlc : std_logic_vector(3 downto 0);
signal rec_is_rtr : std_logic;
......@@ -274,6 +274,8 @@ entity core_top is
signal rec_crc : std_logic_vector(20 downto 0); --Recieved CRC value
signal rec_esi : std_logic; --Recieved Error state indicator
signal ack_recieved_out : std_logic;
signal rec_dram_word : std_logic_vector(31 downto 0);
signal rec_dram_addr : natural range 0 to 15;
--CRC Interfaces
signal crc_enable : std_logic; --Transition from 0 to 1 erases the CRC and operation holds as long as enable=1
......@@ -344,13 +346,14 @@ begin
sync_control <= sync_control_int;
rec_ident_out <= rec_ident;
rec_data_out <= rec_data;
rec_dlc_out <= rec_dlc;
rec_ident_type_out <= rec_ident_type;
rec_frame_type_out <= rec_frame_type;
rec_is_rtr_out <= rec_is_rtr;
rec_brs_out <= rec_brs;
rec_esi_out <= rec_esi;
rec_dram_word_out <= rec_dram_word;
rec_dram_addr <= rec_dram_addr_out;
rec_message_valid_out <= rec_valid; --Confirmation about valid recieved data for RX Buffer
--rec_message_ack_out --NOTE: HandShake protocol with acknowledge not used in the end
......@@ -419,7 +422,6 @@ begin
tran_frame_valid_in=> tran_frame_valid_in,
tran_data_ack => tran_data_ack,
rec_data => rec_data,
rec_ident => rec_ident,
rec_dlc => rec_dlc,
rec_is_rtr => rec_is_rtr,
......@@ -428,6 +430,8 @@ begin
rec_brs => rec_brs,
rec_crc => rec_crc,
rec_esi => rec_esi,
rec_dram_word => rec_dram_word,
rec_dram_addr => rec_dram_addr,
OP_state => OP_state,
arbitration_lost => arbitration_lost,
......@@ -440,7 +444,7 @@ begin
CRC_Error => CRC_Error,
ack_Error => ack_Error,
unknown_state_Error => unknown_state_Error,
bit_stuff_Error_valid =>bit_stuff_Error_valid,
bit_stuff_Error_valid => bit_stuff_Error_valid,
inc_one => inc_one,
inc_eight => inc_eight,
......
......@@ -89,6 +89,15 @@ use work.CANconstants.all;
-- 12.1.2017 1. Added CRC fix for ISO FD CAN. CRC was stopped before the stuff count field. Due to this
-- Stuff count was not included into CRC which made the calculated CRC always wrong!
-- 2. Fixed CRC length for small FD frames to be always 17 instead of 15!
-- 29.11.2017 1. Optimized storing of received data. Data stored into 16*32 RAM (array) after each byte was
-- received. Since RX Buffer is reading the data serially, it does not need to have
-- the data available in parallel! Removed signal "rec_data_r" and replaced it with "rec_dram".
-- RX buffer now provides address signal which combinationally reads the data on RAM output!
-- This approach saved approx. 1000 LC combinationals of Altera device. No RAM was inferred,
-- and the memory was stored in LUT combinational memory! An additional effect of this change
-- is that Received Data are not erased in the SOF of next frame and thus it stays on the output
-- of CAN Core until it is rewritten by next data.
--
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
......@@ -126,7 +135,6 @@ entity protocolControl is
-------------------------
--Recieved data output --
-------------------------
signal rec_data :out std_logic_vector(511 downto 0);
signal rec_ident :out std_logic_vector(28 downto 0);
signal rec_dlc :out std_logic_vector(3 downto 0);
signal rec_is_rtr :out std_logic;
......@@ -136,6 +144,10 @@ entity protocolControl is
signal rec_crc :out std_logic_vector(20 downto 0); --Recieved CRC value
signal rec_esi :out std_logic; --Recieved Error state indicator
--Added interface for aux SRAM
signal rec_dram_word :out std_logic_vector(31 downto 0);
signal rec_dram_addr :in natural range 0 to 15;
--------------------------------
--Operation mode FSM Interface--
--------------------------------
......@@ -302,7 +314,6 @@ entity protocolControl is
---------------------------
--Recieved data registers--
---------------------------
signal rec_data_r : std_logic_vector(511 downto 0);
signal rec_ident_r : std_logic_vector(28 downto 0);
signal rec_dlc_r : std_logic_vector(3 downto 0);
signal rec_is_rtr_r : std_logic;
......@@ -349,6 +360,15 @@ entity protocolControl is
signal stl_pointer : natural range 0 to 3; --Pointer for transcieving the stuf length field
signal data_size : natural range 0 to 511;
-- Signals for optimalization of data reception usage
-- Refer to Revision comment: 29.11.2017
type rec_data_RAM_type is array (0 to 15) of std_logic_vector(31 downto 0);
signal rec_data_sr : std_logic_vector(7 downto 0); --Shift register for data reception
signal rec_dram_ptr : natural range 0 to 7; --Register for counting received bytes in shift register
signal rec_dram_bind : natural range 0 to 3; --Byte index into RAM
signal rec_dram : rec_data_RAM_type;
-----------------------
--CRC field registers--
-----------------------
......@@ -448,7 +468,6 @@ begin
sync_control <= sync_control_r;
--Recieved data registers to output propagation
rec_data <= rec_data_r;
rec_ident <= rec_ident_r;
rec_dlc <= rec_dlc_r;
rec_is_rtr <= rec_is_rtr_r;
......@@ -486,6 +505,11 @@ begin
stuff_parity <= '0' when (dst_ctr mod 2)=0 else
'1';
-------------------------------------
-- Output of receive data RAM
-------------------------------------
rec_dram_word <= rec_dram(rec_dram_addr);
---------------------------------------
---------------------------------------
--Protocol control process
......@@ -563,13 +587,17 @@ begin
data_size <= 0;
--Nulling recieve registers
rec_data_r <= (OTHERS=>'0');
rec_ident_r <= (OTHERS=>'0');
rec_dlc_r <= (OTHERS=>'0');
rec_is_rtr_r <= '0';
rec_ident_type_r <= '0';
rec_frame_type_r <= '0';
-- Receive data RAM
rec_dram_ptr <= 0;
rec_dram_bind <= 0;
rec_data_sr <= (OTHERS => '0');
--Presetting the sampling point control
sp_control_r <= NOMINAL_SAMPLE;
ssp_reset_r <= '0';
......@@ -610,7 +638,6 @@ begin
fixed_destuff_r <= fixed_destuff_r;
destuff_length_r <= destuff_length_r;
stuff_error_enable_r <= stuff_error_enable_r;
rec_data_r <= rec_data_r;
rec_ident_r <= rec_ident_r;
rec_dlc_r <= rec_dlc_r;
rec_is_rtr_r <= rec_is_rtr_r;
......@@ -687,6 +714,10 @@ begin
rx_parity <= rx_parity;
rx_count_grey <= rx_count_grey;
rec_data_sr <= rec_data_sr;
rec_dram_ptr <= rec_dram_ptr;
rec_dram_bind <= rec_dram_bind;
if(drv_ena='0')then
PC_State <= off;
......@@ -781,7 +812,6 @@ begin
crc_enable_r <= '1';
--Erasing the recieved data registers
rec_data_r <= (OTHERS =>'0');
rec_ident_r <= (OTHERS =>'0');
rec_dlc_r <= (OTHERS =>'0');
rec_is_rtr_r <= '0';
......@@ -1258,10 +1288,17 @@ begin
PC_State <= error;
FSM_preset <= '1';
end case;
data_pointer <= 511;
if(OP_State=transciever and tran_frame_type=FD_CAN)then
sync_control_r <= NO_SYNC; --Transmitter shall not synchronize in data phase of CAN FD Frame!
end if;
--Receive RAM signals
rec_dram_ptr <= 0;
rec_dram_bind <= 0;
rec_data_sr <= (OTHERS => '0');
else
if(OP_State=transciever)then
......@@ -1273,9 +1310,31 @@ begin
end if;
if(rec_trig='1')then --Recieving data (also transmitter recieves the same data)
rec_data_r(data_pointer) <= data_rx;
-- Shift register and storing to local RAM
rec_data_sr <= rec_data_sr(6 downto 0)&data_rx;
rec_dram_ptr <= (rec_dram_ptr+1) mod 8;
-- If the whole byte was received
if (rec_dram_ptr=7) then