Commit c62fa03f authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Merge branch '336-feature-tests-extension' into 'master'

Resolve "Feature tests extension"

Closes #336

See merge request !294
parents e3dbe66b a3eeb326
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......@@ -502,7 +502,7 @@ Version 2.2, Commit:
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="12" columns="4">
<lyxtabular version="3" rows="13" columns="4">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="1.5cm">
<column alignment="center" valignment="top" width="2cm">
......@@ -934,7 +934,7 @@ Clarify TXT buffer behaviour when node goes bus-off.
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
......@@ -943,7 +943,7 @@ Clarify TXT buffer behaviour when node goes bus-off.
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
......@@ -952,7 +952,7 @@ Ondrej Ille
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
......@@ -961,7 +961,7 @@ Ondrej Ille
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
......@@ -969,6 +969,46 @@ Clarify Bus-off behaviour aftet Start-up.
Clarify that frame must be inserted to TXT Buffer before sending.
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
2.2.3
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Ondrej Ille
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
18-11-2019
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Clarify behaviour of Transmitter delay measurement.
Add notes on RX frame timestamping.
Extend SSP position to 255.
\end_layout
\end_inset
</cell>
</row>
......@@ -2297,10 +2337,6 @@ s of the fact if bit rate is switched in current frame) on recessive to
dominant edge between FDF (EDL) and r0 bits.
Transmitter delay is readable after its measurement from TRV_DELAY register.
Transmitter delay is measured in periods of System clock.
Note that measured transmitter delay of CTU CAN FD includes input time
of CTU CAN FD which is 2 clock periods of System clock.
Therefore value read from TRV_DELAY register, will be higher than actual
delay from can_tx to can_rx by 2 clock periods of System clock.
\end_layout
\begin_layout Standard
......@@ -2347,6 +2383,22 @@ name "fig:transmitter-delay"
\end_layout
\begin_layout Description
Note Transmitter delay measurement includes input delay of CTU CAN FD (which
is 2 clock periods of System clock).
Therefore measured transmitter delay will be always higher by two than
actual delay from can_tx to can_rx (e.g.
if signal propagation from can_tx to can_rx takes 110 ns (11 System clock
periods at 100 MHz), measured transmitter delay will be 13).
\end_layout
\begin_layout Description
Note Transmitter delay measurement is saturated to 127 System clock periods.
If the delay between can_tx and can_rx is longer, only 127 will be measured.
When system clock frequency is 100 Mhz, this gives 1,27 us of maximal measurabl
e transmitter delay which is more than most of CAN transceivers need.
\end_layout
\begin_layout Subsection
Secondary sampling point
\end_layout
......@@ -2356,8 +2408,9 @@ Secondary sampling point is used by transmitters during data bit rate to
detect bit errors.
Its position is configured as delay from start of bit time (Sync_Seg) in
multiples of System clock (NOT time quanta!).
Secondary sampling point position can be fixed, given by Transmitter delay,
or it can be disabled as is shown in Figure
Secondary sampling point position can be fixed (SSP Offset only), derived
from Transmitter delay (SSP Offset + Transmitter delay), or it can be disabled
(No SSP) as is shown in Figure
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:secondary-sampling-point"
......@@ -2371,12 +2424,6 @@ noprefix "false"
When Secondary sampling point is disabled, regular sampling point as configured
by BRP_FD register is used by transmitters during data bit rate for bit
error detection.
Secondary sampling point position is configurable between 0 - 127.
If Secondary sampling point is configured to more than 127 (e.g.
as result of large measured Transmitter delay), it is saturated to 127.
Note that since CTU CAN FD input delay is 2 System clock periods (minimum
time quanta), position of Secondary sampling point shall be configured
to at least 2 to compensate its own input delay.
\end_layout
\begin_layout Standard
......@@ -2423,6 +2470,68 @@ name "fig:secondary-sampling-point"
\end_layout
\begin_layout Standard
\begin_inset Float figure
placement h
wide false
sideways false
status open
\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
filename ../pics/Visio_generated/SSP_timing.pdf
lyxscale 20
scale 90
\end_inset
\end_layout
\begin_layout Plain Layout
\begin_inset Caption Standard
\begin_layout Plain Layout
Secondary sampling point 2
\begin_inset CommandInset label
LatexCommand label
name "fig:secondary-sampling-point-2"
\end_inset
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Description
Note Secondary sampling point offset (SSP_CFG[SSP_OFFSET]) is configurable
between 0 - 255.
Internal range of secondary sampling point position is also 0 - 255.
If due to some reason secondary sampling point position would be more than
255 clock cycles from start of bit (e.g.
due to large measured Transmitter delay) it is saturated to 255.
\end_layout
\begin_layout Description
Note Since CTU CAN FD input delay is 2 System clock periods (minimum time
quanta), position of Secondary sampling point shall be configured to at
least 2 to compensate its own input delay (therefore if SSP_CFG[SSP_OFFSET]
< 3 and SSP_CFG[SSP_SRC] = SSP_SRC_OFFSET], it is impossible to transmitt
CAN FD frames without detecting bit error on CTU CAN FDs own transmitted
frame).
\end_layout
\begin_layout Subsection
CAN FD support
\end_layout
......@@ -2456,7 +2565,7 @@ System clock period is equal to minimal time quanta.
e by CTU CAN FD is 2 time quanta (value of information processing time).
Minimal duration of Sync_Seg + Prop_Seg + Phase1_Seg is also 2 time quanta.
This can be achieved by: Prop_Seg = 0 and Phase1_Seg = 1, or Prop_Seg =
1 and Phase1_Seg = 2.
1 and Phase1_Seg = 0.
Such configuration is possible for both nominal and data bit rate.
Note that this is absolute maximum rating, and therefore allows very little
flexibility in bit rate configuration.
......@@ -3081,6 +3190,8 @@ Note
If during this time Set ready command is sent to TXT buffer, TXT buffer
immediately moves to Aborted state (since node is bus-off and all TXT buffers
in TX ready move to Aborted when CTU CAN FD is bus-off).
SW shall wait until node is Error active (either polling or via FCS Interrupt)
before issuing Set Ready command to any TXT buffer.
\end_layout
\begin_layout Description
......@@ -3093,6 +3204,16 @@ Note
buffer with valid CAN frame for transmission.
\end_layout
\begin_layout Description
Note
\begin_inset space ~
\end_inset
3 CTU CAN FD only transmitts only reactive Overload frames.
There are no internal conditions in CTU CAN FD which would cause transmission
of Overload frame.
\end_layout
\begin_layout Section
CAN frame reception
\end_layout
......@@ -3253,6 +3374,21 @@ RX buffer can be flushed (Release RX buffer) by writing logic 1 to COMMAND[RRB]
not stored to RX buffer.
\end_layout
\begin_layout Subsection
Timestamping
\end_layout
\begin_layout Standard
Timestamp of received CAN frame is stored during CAN frame reception.
When reading received CAN frame from RX buffer, timestamp can be read from
TIMESTAMP_L_W, TIMESTAMP_U_W memory words.
It is possible to configure whether timestamp for received frame will be
taken in sample point of Start of Frame bit or in 6th bit of End of Frame
(moment when received CAN frame is considered valid according to CAN FD
specification).
This setting is given by RX_SETTINGS[RTSOP].
\end_layout
\begin_layout Subsection
Frame filtering
\end_layout
......@@ -3702,7 +3838,7 @@ In self test mode CTU CAN FD considers transmitted frame valid even if does
\end_layout
\begin_layout Subsection
Acknowledge forbidden mode
XAcknowledge forbidden mode
\end_layout
\begin_layout Standard
......
......@@ -1122,10 +1122,12 @@ When CTU CAN FD GIT repository is clonned, register map can be generated
\end_layout
 
\begin_layout Verbatim
cd scripts
\end_layout
 
\begin_layout Verbatim
./update_reg_map
\end_layout
 
......@@ -1138,10 +1140,12 @@ Documentation can be exported from VHDL RTL codes by following script:
\end_layout
 
\begin_layout Verbatim
cd scripts
\end_layout
 
\begin_layout Verbatim
python gen_lyx_tables.py --configPath vhdl_lyx_interface_cfg.yml
\end_layout
 
......@@ -1174,10 +1178,12 @@ CTU CAN FD contains release tags in GIT repository.
\end_layout
 
\begin_layout Verbatim
cd scripts
\end_layout
 
\begin_layout Verbatim
python create_release.py --output_dir ../release_directory_name
\end_layout
 
......@@ -1199,10 +1205,12 @@ src/component.xml
\end_layout
 
\begin_layout Verbatim
cd scripts
\end_layout
 
\begin_layout Verbatim
python gen_vivado_component.py
\end_layout
 
......@@ -9590,6 +9598,10 @@ bus off
CAN Core
\end_layout
 
\begin_layout Description
File: can_core.vhd
\end_layout
\begin_layout Standard
CAN Core implements following functionality:
\end_layout
......@@ -9814,6 +9826,10 @@ filename "entity_docs/can_core.lyx"
Protocol control
\end_layout
 
\begin_layout Description
File: protocol_control.vhd
\end_layout
\begin_layout Standard
Protocol control implements following functionality:
\end_layout
......@@ -9991,6 +10007,10 @@ filename "entity_docs/protocol_control.lyx"
Protocol control FSM
\end_layout
 
\begin_layout Description
File: protocol_control_fsm.vhd
\end_layout
\begin_layout Standard
Protocol control FSM implements following functionality:
\end_layout
......@@ -10402,6 +10422,10 @@ name "fig:Protocol-control-FSM"
Control counter
\end_layout
 
\begin_layout Description
File: control_counter.vhd
\end_layout
\begin_layout Standard
Control counter measures duration of CAN frame fields which last longer
than 1 bit.
......@@ -10984,6 +11008,10 @@ name "fig:arbitration-lost-capture"
Retransmitt counter
\end_layout
 
\begin_layout Description
File: retransmitt_counter.vhd
\end_layout
\begin_layout Standard
Retransmitt counter controls number of
\color red
......@@ -11488,6 +11516,10 @@ name "subsec:Reintegration-counter"
 
\end_layout
 
\begin_layout Description
File: reintegration_counter.vhd
\end_layout
\begin_layout Standard
Reintegration counter counts 128 consecutive ocurrences of 11 consecutive
......@@ -11939,6 +11971,10 @@ name "subsec:TX-Shift-Register"
 
\end_layout
 
\begin_layout Description
File: tx_shift_reg.vhd
\end_layout
\begin_layout Standard
TX shift register is 32 bit shift register which transmitts given bit sequence
to the output of Protocol control module.
......@@ -13440,6 +13476,10 @@ name "subsec:RX-Shift-Register"
 
\end_layout
 
\begin_layout Description
File: rx_shift_reg.vhd
\end_layout
\begin_layout Standard
RX shift register is 32 bit shift register which receives bit sequence and
stores parts of this sequence to dedicated capture registers when commanded
......@@ -15777,6 +15817,10 @@ name "subsec:Error-detector"
 
\end_layout
 
\begin_layout Description
File: err_detector.vhd
\end_layout
\begin_layout Standard
Error detector processes errors detected by other modules, decides whether
these errors are valid and creates error frame request to Protocol control
......@@ -16772,7 +16816,7 @@ status open
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="6" columns="2">
<lyxtabular version="3" rows="7" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="30.5line%">
<column alignment="left" valignment="top" width="63line%">
......@@ -16871,7 +16915,13 @@ r1
\color inherit
bit in frame with
\color red
extended identifier
extended identifier
\color inherit
or
\color red
r0
\color inherit
bit in CAN FD frames
\end_layout
 
\end_inset
......@@ -16889,6 +16939,10 @@ recessive
form error
\color inherit
is detected.
Recessive bit would mean extending beyond CAN FD standard (CAN XL).
This is not supported.
Protocol exception is not implemented on further extensions beyond CAN
FD protocol.
\end_layout
 
\end_inset
......@@ -16900,10 +16954,31 @@ form error
 
\begin_layout Plain Layout
 
\color red
EDL
\color inherit
/
\color red
r0
\color inherit
bit in CAN FD frames
bit in CAN frames with
\color red
base identifier
\color inherit
.
\color red
EDL
\color inherit
/
\color red
r1
\color inherit
bit in CAN FD frames with
\color red
extended identifier
\color inherit
.
\end_layout
 
\end_inset
......@@ -16916,13 +16991,12 @@ If
\color red
recessive
\color inherit
bit is received,
bit is received and CAN FD support is disabled MODE[FDE] = '0',
\color red
form error
\color inherit
is detected.
Protocol exception is not implemented on further extensions beyond CAN
FD protocol.
Recessive bit here indicates CAN FD frame.
\end_layout
 
\end_inset
......@@ -16940,10 +17014,6 @@ CRC delimiter
,
\color red
ACK delimiter
\color inherit
,
\color red
EOF
\end_layout
 
\end_inset
......@@ -16963,6 +17033,38 @@ form error
is detected.
\end_layout
 
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
\color red
EOF
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
If
\color red
dominant
\color inherit
bit is detected at all but last bit of EOF, form Error is detected.
At last bit
\color red
dominant
\color inherit
bit means Error frame only for transmitter.
For receiver, it means Overload condition.
\end_layout
\end_inset
</cell>
</row>
......@@ -17787,6 +17889,10 @@ name "fig:crc-check"
Operation control
\end_layout
 
\begin_layout Description
File: operation_control.vhd
\end_layout
\begin_layout Standard
Operation control implements following functionality:
\end_layout
......@@ -18586,6 +18692,10 @@ name "tab:operation-control-state-transitions"
Fault confinement
\end_layout
 
\begin_layout Description
File: fault_confinement.vhd
\end_layout
\begin_layout Standard
Fault confinement module implements following functionality:
\end_layout
......@@ -19201,6 +19311,10 @@ h) After the successful reception of a frame (reception without error up
Bit stuffing
\end_layout
 
\begin_layout Description
File: bit_stuffing.vhd
\end_layout
\begin_layout Standard
Bit stuffing module implements following functionality:
\end_layout
......@@ -20037,6 +20151,10 @@ name "subsec:Bit-Destuffing"
 
\end_layout
 
\begin_layout Description
File: bit_destuffing.vhd
\end_layout
\begin_layout Standard
Bit destuffing module implements following functionality:
\end_layout
......@@ -20823,6 +20941,10 @@ name "tab:bit-destuffing-operation"
CAN CRC
\end_layout
 
\begin_layout Description
File: can_crc.vhd
\end_layout
\begin_layout Standard
CAN CRC implements following functionality:
\end_layout
......@@ -21742,6 +21864,10 @@ name "tab:can-crc-enable-signals"
Trigger multiplexor
\end_layout
 
\begin_layout Description
File: trigger_mux.vhd
\end_layout
\begin_layout Standard
Trigger multiplexor implements following functionality:
\end_layout
......@@ -22210,6 +22336,10 @@ name "subsec:Bus-traffic-counters"
 
\end_layout
 
\begin_layout Description
File: bus_traffic_counters.vhd
\end_layout
\begin_layout Standard