Commit c5391d8d authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Extend wave files.

parent c4bb605f
[*]
[*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI
[*] Thu Jan 2 18:32:03 2020
[*] Fri Jan 3 10:32:41 2020
[*]
[dumpfile] "/build/test/build/vunit_out/test_output/lib.tb_feature.err_capt_sof_284efd78b8ceccd5c281a9a4579b7829b1e15644/ghdl/wave.ghw"
[dumpfile_mtime] "Thu Jan 2 18:29:52 2020"
[dumpfile_size] 2110746
[dumpfile] "/build/test/build/vunit_out/test_output/lib.tb_feature.err_capt_data_bit_36b01b910468ea45d39f50386a4eb5ab54cd6ffa/ghdl/wave.ghw"
[dumpfile_mtime] "Fri Jan 3 10:32:41 2020"
[dumpfile_size] 106249708
[savefile] "/build/test/wave_files/feature_err_capt_sof.gtkw"
[timestart] 19692000000
[timestart] 35010000000
[size] 1853 1025
[pos] -1 -1
*-29.000000 21290000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] -101 -101
*-31.000000 40944094000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.tb_feature.
[treeopen] top.tb_feature.test_comp.
[treeopen] top.tb_feature.test_comp.g_inst[1].
[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.
[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.
[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.
[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.
[treeopen] top.tb_feature.test_comp.g_inst[2].
[treeopen] top.tb_feature.test_comp.g_inst[2].can_inst.
[treeopen] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.
[treeopen] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.operation_control_inst.
[treeopen] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.protocol_control_inst.
[sst_width] 399
[signals_width] 262
[sst_expanded] 1
[sst_vpaned_height] 300
[sst_vpaned_height] 629
@200
-Node 1
@28
top.tb_feature.test_comp.g_inst[1].can_inst.can_tx
top.tb_feature.test_comp.g_inst[1].can_inst.can_rx
@420
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.curr_state
@28
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.pc_rx_trigger
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.tx_trigger
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.err_frm_req
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.is_sof
@22
#{top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[7:0]} top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[7] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[6] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[5] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[4] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[3] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[2] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[1] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[0]
@28
#{top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_type_q[2:0]} top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_type_q[2] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_type_q[1] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_type_q[0]
@29
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_frm_req_i
@22
#{top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[4:0]} top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[4] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[3] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[2] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[1] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[0]
@420
top.tb_feature.test_comp.bl_force
@28
top.tb_feature.test_comp.bl_inject
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.form_err
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.bit_err
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.rec_is_rtr
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.is_data
@200
-Node 2
@28
top.tb_feature.test_comp.g_inst[2].can_inst.can_rx
top.tb_feature.test_comp.g_inst[2].can_inst.can_tx
@420
top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.curr_state
@421
top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.operation_control_inst.curr_state
[pattern_trace] 1
[pattern_trace] 0
[*]
[*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI
[*] Fri Dec 13 11:57:51 2019
[*] Fri Dec 27 13:44:55 2019
[*]
[dumpfile] "/build/test/build/vunit_out/test_output/lib.tb_feature.error_rules_f_tx_b7c201f1e18a15862c8c6d7c155d24926810ff5a/ghdl/wave.ghw"
[dumpfile_mtime] "Fri Dec 13 11:56:34 2019"
[dumpfile_size] 12182076
[dumpfile] "/build/test/build/vunit_out/test_output/lib.tb_feature.err_norm_fd_0fc3bbf5be66798fd69c97a472f061ce25ac86af/ghdl/wave.ghw"
[dumpfile_mtime] "Fri Dec 27 12:33:41 2019"
[dumpfile_size] 11285180
[savefile] "/build/test/wave_files/feature_error_rules.gtkw"
[timestart] 120000000000
[timestart] 262580000000
[size] 1853 1025
[pos] -1 -1
*-35.000000 102280000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-33.476460 303670000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.tb_feature.
[treeopen] top.tb_feature.mem_bus.
[treeopen] top.tb_feature.test_comp.
[treeopen] top.tb_feature.test_comp.g_inst[1].
[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.
[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.
[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.
[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.
[treeopen] top.tb_feature.test_comp.g_inst[2].
[treeopen] top.tb_feature.test_comp.g_inst[2].can_inst.
[treeopen] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.
[treeopen] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.protocol_control_inst.
[sst_width] 389
[signals_width] 320
[signals_width] 331
[sst_expanded] 1
[sst_vpaned_height] 599
[sst_vpaned_height] 629
@28
top.tb_feature.test_comp.g_inst[2].can_inst.clk_sys
@420
top.tb_feature.test_comp.loop_ctr
@200
-Node 1
@28
top.tb_feature.test_comp.g_inst[1].can_inst.can_rx
top.tb_feature.test_comp.g_inst[1].can_inst.can_tx
[color] 1
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.rx_data_nbs
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.rx_data_wbs
[color] 1
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.tx_data_wbs
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.ctrl_ctr_zero
@420
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.operation_control_inst.curr_state
@28
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.tx_trigger
top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.sample_sec
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.data_halt
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.ide_is_arbitration
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.tran_ident_type
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.is_receiver
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.is_arbitration_i
@29
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.bit_err_enable
@420
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.operation_control_inst.curr_state
@22
#{top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.ctrl_ctr_q[8:0]} top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.ctrl_ctr_q[8] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.ctrl_ctr_q[7] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.ctrl_ctr_q[6] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.ctrl_ctr_q[5] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.ctrl_ctr_q[4] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.ctrl_ctr_q[3] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.ctrl_ctr_q[2] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.ctrl_ctr_q[1] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.control_counter_inst.ctrl_ctr_q[0]
@28
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.rx_trigger
top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.bit_err_arb_i
top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst.bit_err_ssp_condition
top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst.bit_err_ssp_capt_q
#{top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.sp_control[1:0]} top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.sp_control[1] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.sp_control[0]
@420
top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.curr_state
@28
top.tb_feature.test_comp.g_inst[2].can_inst.bus_sampling_inst.sample_sec
@22
#{top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[8:0]} top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[8] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[7] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[6] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[5] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[4] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[3] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[2] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[1] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[0]
@24
......@@ -48,10 +77,17 @@ top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.
top.tb_feature.test_comp.g_inst[2].can_inst.can_rx
top.tb_feature.test_comp.g_inst[2].can_inst.can_tx
@420
top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.operation_control_inst.curr_state
top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.curr_state
@24
#{top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[8:0]} top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[8] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[7] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[6] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[5] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[4] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[3] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[2] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[1] top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.fault_confinement_inst.err_counters_inst.rx_err_ctr_q[0]
@29
@28
top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.protocol_control_inst.rx_trigger
@420
top.tb_feature.test_comp.bl_force
@28
top.tb_feature.test_comp.bl_inject
top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.crc_err
top.tb_feature.test_comp.g_inst[2].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.ack_err
[pattern_trace] 1
[pattern_trace] 0
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