Commit c3eda0bd authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

clean-up remove obsolete files!

parent 480d7db6
This diff is collapsed.
This diff is collapsed.
#LyX 2.2 created this file. For more info see http://www.lyx.org/
\lyxformat 508
\begin_document
\begin_header
\save_transient_properties true
\origin unavailable
\textclass IEEEtran
\begin_preamble
\usepackage{fancyhdr}
\renewcommand{\headrulewidth}{0pt}
\end_preamble
\use_default_options true
\begin_modules
eqs-within-sections
figs-within-sections
customHeadersFooters
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\end_header
\begin_body
\begin_layout Title
\begin_inset space ~
\end_inset
\begin_inset Newline newline
\end_inset
CAN FLEXIBLE DATA-RATE
\begin_inset Newline newline
\end_inset
IP CORE
\begin_inset Newline newline
\end_inset
\size large
PRODUCT BRIEF
\end_layout
\begin_layout Standard
\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
thispagestyle{fancy}
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\end_inset
\end_layout
\begin_layout Left Header
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="2">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="0pt">
<column alignment="left" valignment="top" width="0pt">
<row>
<cell multirow="3" alignment="left" valignment="middle" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Graphics
filename E:/Skola/CVUT-FEL/LEV.bmp
scale 14
\end_inset
\end_layout
\end_inset
</cell>
<cell alignment="left" valignment="top" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
\series bold
Czech Technical University in Prague
\end_layout
\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="center" valignment="top" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
</cell>
<cell alignment="left" valignment="top" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Faculty of electrical engineering
\end_layout
\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="center" valignment="top" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
</cell>
<cell alignment="left" valignment="top" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Department of measurement
\end_layout
\end_inset
</cell>
</row>
</lyxtabular>
\end_inset
\end_layout
\begin_layout Right Header
Ondrej Ille
\begin_inset Newline newline
\end_inset
August 2016
\end_layout
\begin_layout Section*
Overview
\end_layout
\begin_layout Standard
CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
1.0 and ISO CAN FD specification in single light-weight IP Core.
It is soft-core IP Core written in VHDL with only standard IEEE libraries
needed.
The main target of usage are FPGA applications and the core is available
as RTL.
It is optimized for inference of native hardware blocks such as SRAM memories
and multipliers in DSP blocks.
Generic settings achieve a high level of flexibility before synthesis.
It is posible to balance the core between high amount of features and small
size.
\end_layout
\begin_layout Standard
The IP Core is accessed as memory mapped peripheria via Avalon bus.
Easy manipulation with the core is achieved by using hardware buffers for
CAN frames.
One FIFO like RX buffer is available and two TX buffers are available.
Timestamps can be captured for various events on the CAN bus.
Additionally transmission of CAN frames can be triggered by external timestamp.
Asynchronous access is supported via rich interrupt settings.
Three Bit filters and one Range filter is available on received frames.
\end_layout
\begin_layout Standard
The design is fully tested at RTL level as well as in real hardware with
Altera Cyclone IV FPGA series.
The automated test-framework in TCL is available within the core and it
provides an easy way of reproducing unit test, feature covering tests and
real bus simulation.
\end_layout
\begin_layout Standard
\begin_inset VSpace bigskip
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open
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\noindent
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\begin_inset space ~
\end_inset
\begin_inset space ~
\end_inset
\begin_inset space ~
\end_inset
\begin_inset space ~
\end_inset
\begin_inset space ~
\end_inset
\begin_inset Graphics
filename E:/Skola/CVUT-FEL/Testovaci Platforma/Obrazky/IP_core_linkedin.jpg
lyxscale 10
scale 55
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Section*
Features
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
CAN 2.0, CAN FD 1.0 and ISO CAN FD
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
RTL VHDL (synthesis), TCL (testing)
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Pre-synthesis configurable features
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Avalon memory bus
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Timestamping and transmission at given time
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Optional event and error logging
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Fault confinement state manipulation
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Transceiver delay measurement
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Size 6 000 - 11 000 LUTs
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
2 000 - 12 000 SRAM memory bits
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Synchronization output with time quantum
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Variety of interrupt sources
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Filtering of received frame
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Listen-only mode, Self-test mode,
\begin_inset Newline newline
\end_inset
Acknowledge forbidden mode
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Up to 14 Mbit in
\begin_inset Quotes eld
\end_inset
Data
\begin_inset Quotes erd
\end_inset
bit-rate
\begin_inset Newline newline
\end_inset
(with 100 Mhz Core clock)
\end_layout
\begin_layout Itemize
\paragraph_spacing onehalf
Driver in C available
\end_layout
\end_body
\end_document
################################################################################
##
## CAN with Flexible Data-Rate IP Core
##
## Copyright (C) 2017 Ondrej Ille <ondrej.ille@gmail.com>
##
## Project advisor: Jiri Novak <jnovak@fel.cvut.cz>
## Department of Measurement (http://meas.fel.cvut.cz/)
## Faculty of Electrical Engineering (http://www.fel.cvut.cz)
## Czech Technical University (http://www.cvut.cz/)
##
## Permission is hereby granted, free of charge, to any person obtaining a copy
## of this VHDL component and associated documentation files (the "Component"),
## to deal in the Component without restriction, including without limitation
## the rights to use, copy, modify, merge, publish, distribute, sublicense,
## and/or sell copies of the Component, and to permit persons to whom the
## Component is furnished to do so, subject to the following conditions:
##
## The above copyright notice and this permission notice shall be included in
## all copies or substantial portions of the Component.
##
## THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
## AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
## FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
## IN THE COMPONENT.
##
## The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
## Anybody who wants to implement this IP core on silicon has to obtain a CAN
## protocol license from Bosch.
##
################################################################################
################################################################################
## Description:
## CAN FD IP Core testbench TCL framework for automatic
## test execution
##
################################################################################
puts "----------------------------------"
puts "--Starting CANTest TCL framework--"
puts "----------------------------------"
#Check if environment variables are existing
quietly set exist_var [info exist ITERATIONS]
# IP Core standalone relative location
quietly set BASE_DIR "../"
quietly set BASE_TEST "../test"
# Test platform relative location
#quietly set BASE_DIR "../../../CAN_FD_IP_Core/"
#quietly set BASE_TEST "../../../CAN_FD_IP_Core/test"
# Create the environment if not yet existant
if { $exist_var == 0 } {
puts "Enviroment variables not found -> Setting up environment"
puts ""
do [file join $BASE_TEST set_env.tcl]
}
#Include the library functions
source [file join $BASE_TEST lib/test_lib.tcl]
puts ""
puts "Welcome in CAN FD IP Core TCL test framework"
puts "use: 'help' command to obtain list of available commands"
puts ""
quietly set FRAMEWORK_QUIT false
# Test parser loop
while { $FRAMEWORK_QUIT == false } {
set arg1 ""
set arg2 ""
set arg3 ""
set arg4 ""
set arg5 ""
scan [gets stdin] "%s %s %s %s %s" arg1 arg2 arg3 arg4 arg5
if { $arg1 == "exit" } {
quietly set FRAMEWORK_QUIT true
} elseif { $arg1 == "help" } {
print_help
} elseif { $arg1 == "test" } {
if { $arg2 == "unit" } {
if { $arg3 == "all" } {
exec_all_TCL_from_path [file join $BASE_TEST unit ]
} else {
exec_TCL_from_path [file join $BASE_TEST unit $arg3]
}
} elseif { $arg2 == "sanity" } {
if { $arg3 == "run" } {
run_sanity
} elseif { $arg3 == "start" } {
quietly set SILENT_SANITY "false"
if { $arg4 == "silent" } {
quietly set SILENT_SANITY "true"
}
start_sanity
} else {
puts "Unknown command! Type: 'help' to obtain list of commands!"
}
} elseif { $arg2 == "feature" } {
if { $arg3 == "start" } {
start_feature_FIFO
} elseif { $arg3 == "run" } {
run_feature_FIFO
} elseif { $arg3 == "print_config" } {
show_feature_FIFO
} else {
puts "Unknown command! Type: 'help' to obtain list of commands!"
}
} else {
puts "Unknown command! Type: 'help' to obtain list of commands!"
}
} else {
puts "Unknown command! Type: 'help' to obtain list of commands!"
}
}
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[*]
[*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI
[*] Thu Jun 13 18:12:55 2019
[*]
[dumpfile] "/build/test/build/vunit_out/test_output/lib.tb_presc_unit_test.all_36c0061843e0ce1efaf3b4915621b15ccda4fdb8/ghdl/wave.ghw"
[dumpfile_mtime] "Thu Jun 13 17:58:26 2019"
[dumpfile_size] 149288119
[savefile] "/build/test/presc_waves.gtkw"
[timestart] 45099500000000
[size] 1853 1025
[pos] -1 -1
*-36.782135 45734230000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.tb_presc_unit_test.
[treeopen] top.tb_presc_unit_test.tb.
[treeopen] top.tb_presc_unit_test.tb.i_test.
[treeopen] top.tb_presc_unit_test.tb.i_test.prescaler_comp.
[treeopen] top.tb_presc_unit_test.tb.i_test.prescaler_comp.segment_end_detector_inst.
[treeopen] top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.
[sst_width] 442
[signals_width] 249
[sst_expanded] 1
[sst_vpaned_height] 629
@28
top.tb_presc_unit_test.tb.i_test.prescaler_comp.res_n
top.tb_presc_unit_test.tb.i_test.prescaler_comp.clk_sys
@420
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.bt_fsm_i
top.tb_presc_unit_test.tb.i_test.prescaler_comp.bit_time_fsm_inst.current_state
top.tb_presc_unit_test.tb.i_test.loop_ctr
@28
top.tb_presc_unit_test.tb.i_test.prescaler_comp.drv_ena
top.tb_presc_unit_test.tb.i_test.sync_nbt
top.tb_presc_unit_test.tb.i_test.sample_nbt
top.tb_presc_unit_test.tb.i_test.sample_dbt
top.tb_presc_unit_test.tb.i_test.prescaler_comp.tx_trigger
top.tb_presc_unit_test.tb.i_test.prescaler_comp.rx_trig_req
top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.segm_end
top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.resync_edge_valid
@29
top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.h_sync_valid
@28
top.tb_presc_unit_test.tb.i_test.prescaler_comp.segment_end_detector_inst.segm_end_resync_valid
#{top.tb_presc_unit_test.tb.i_test.prescaler_comp.rx_triggers[1:0]} top.tb_presc_unit_test.tb.i_test.prescaler_comp.rx_triggers[1] top.tb_presc_unit_test.tb.i_test.prescaler_comp.rx_triggers[0]
@24
#{top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[9:0]} top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[9] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[8] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[7] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[6] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[5] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[4] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[3] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[2] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[1] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_q[0]
#{top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[9:0]} top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[9] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[8] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[7] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[6] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[5] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[4] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[3] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[2] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[1] top.tb_presc_unit_test.tb.i_test.prescaler_comp.resynchronisation_inst.exp_seg_length_d[0]
#{top.tb_presc_unit_test.tb.i_test.drv_ph1_dbt[4:0]} top.tb_presc_unit_test.tb.i_test.drv_ph1_dbt[4] top.tb_presc_unit_test.tb.i_test.drv_ph1_dbt[3] top.tb_presc_unit_test.tb.i_test.drv_ph1_dbt[2] top.tb_presc_unit_test.tb.i_test.drv_ph1_dbt[1] top.tb_presc_unit_test.tb.i_test.drv_ph1_dbt[0]
#{top.tb_presc_unit_test.tb.i_test.drv_prs_dbt[5:0]} top.tb_presc_unit_test.tb.i_test.drv_prs_dbt[5] top.tb_presc_unit_test.tb.i_test.drv_prs_dbt[4] top.tb_presc_unit_test.tb.i_test.drv_prs_dbt[3] top.tb_presc_unit_test.tb.i_test.drv_prs_dbt[2] top.tb_presc_unit_test.tb.i_test.drv_prs_dbt[1] top.tb_presc_unit_test.tb.i_test.drv_prs_dbt[0]
@22
#{top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[7:0]} top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[7] top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[6] top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[5] top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[4] top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[3] top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[2] top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[1] top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[0]
@28
#{top.tb_presc_unit_test.tb.i_test.sync_control[1:0]} top.tb_presc_unit_test.tb.i_test.sync_control[1] top.tb_presc_unit_test.tb.i_test.sync_control[0]
#{top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.sp_control[1:0]} top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.sp_control[1] top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.sp_control[0]
top.tb_presc_unit_test.tb.i_test.br_shifted
top.tb_presc_unit_test.tb.i_test.prescaler_comp.sync_edge
@420
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tseg1_exp_length
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tseg1_i
@28
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tq_edge_nbt
@420
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tseg2_nbt_i
@24
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tseg2_nbt_exp_length
@420
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tq_ctr_nbt
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tq_ctr_dbt
@24
#{top.tb_presc_unit_test.tb.i_test.drv_ph2_nbt[5:0]} top.tb_presc_unit_test.tb.i_test.drv_ph2_nbt[5] top.tb_presc_unit_test.tb.i_test.drv_ph2_nbt[4] top.tb_presc_unit_test.tb.i_test.drv_ph2_nbt[3] top.tb_presc_unit_test.tb.i_test.drv_ph2_nbt[2] top.tb_presc_unit_test.tb.i_test.drv_ph2_nbt[1] top.tb_presc_unit_test.tb.i_test.drv_ph2_nbt[0]
@22
#{top.tb_presc_unit_test.tb.i_test.drv_ph2_dbt[4:0]} top.tb_presc_unit_test.tb.i_test.drv_ph2_dbt[4] top.tb_presc_unit_test.tb.i_test.drv_ph2_dbt[3] top.tb_presc_unit_test.tb.i_test.drv_ph2_dbt[2] top.tb_presc_unit_test.tb.i_test.drv_ph2_dbt[1] top.tb_presc_unit_test.tb.i_test.drv_ph2_dbt[0]
@420
top.tb_presc_unit_test.tb.i_test.mod_check_enabled
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tseg2_dbt_i
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tseg2_dbt_exp_length
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tseg2_nbt_req
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tseg2_nbt_ack
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tseg2_dbt_req
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tseg2_dbt_ack
@28
top.tb_presc_unit_test.tb.i_test.prescaler_model_comp.tq_edge_dbt
[pattern_trace] 1
[pattern_trace] 0