CAN FD IP Core written in VHDL. Designed to be compliant with ISO1198-1:2015.
Supports ISO and NON-ISO versions of CAN FD protocol.
## License
CTU CAN FD is published under MIT license shown in: []( https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/blob/master/LICENSE)
CTU CAN FD linux driver is published under GPLv2 license.
The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
Anybody who wants to implement this IP core on silicon or FPGA for commercial
purposes has to obtain CAN protocol license from Bosch.
## Design
CTU CAN FD RTL is written in VHDL with no vendor specific libraries/components required.
CTU CAN FD is written with frequent usage of clock enables (FPGA) allowing inferred clock gating.
## Verification
CTU CAN FD verification is done in GHDL + VUnit + GTKWave combination. Verification is done
on RTL (no gate level sims so far...).
Custom GHDL with wave dumping speed-up is used:
[GHDL](https://github.com/Blebowski/ghdl).
Custom Vunit is used which allows starting GTKWave interactively when simulation run starts:
[Vunit](https://github.com/mjerabek/vunit).
There are following types of tests:
Unit tests - own testbench for each module
Feature tests - common testbench
Sanity test - One testbench
Reference test - One testbench
Test architecture is further described in: TODO.
Each test/testbench has common header which is used to collect what has been verified: TODO.
There is PSL functional coverage and PSL assertions available in: [](http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/functional_coverage/functional_coverage_report.html)
For now GCov is used to collect code coverage in GHDL and its results are shown in: