Commit bdfece5c authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '306-synchronization-edge-by-time-quanta' into 'master'

Resolve "Synchronization edge by Time Quanta"

Closes #306

See merge request !296
parents f18cf802 9e36fc2f
Pipeline #13590 passed with stage
in 17 seconds
......@@ -33987,12 +33987,11 @@ can_rx
\series default
are detected with granularity of
\color red
time quanta (
\color blue
This is TODO, so far detected with System clock period, gating by tq_edge
needs to be added
time quanta
\color black
(Edges are gated by Time quanta edge provided by Prescaler)
\color red
).
.
\color black
When CTU CAN FD is running in
......
......@@ -108,7 +108,7 @@ Generics\end_layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="4" rows="7" version="3">
<lyxtabular columns="4" rows="8" version="3">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="3.5cm">
......@@ -215,7 +215,7 @@ Reset polarity\end_layout
\begin_inset Text
\begin_layout Plain Layout
G_SSP_SHIFT_LENGTH\end_layout
G_SSP_DELAY_SAT_VAL\end_layout
\end_inset
</cell>
......@@ -231,7 +231,7 @@ natural\end_layout
\begin_inset Text
\begin_layout Plain Layout
130\end_layout
255\end_layout
\end_inset
</cell>
......@@ -316,6 +316,40 @@ Width (number of bits) in transceiver delay measurement counter\end_layout
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
G_SSP_POS_WIDTH\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
natural\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
8\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Width of SSP position\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
G_USE_SSP_SATURATION\end_layout
......@@ -392,7 +426,7 @@ Ports\end_layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="4" rows="25" version="3">
<lyxtabular columns="4" rows="26" version="3">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
......@@ -1019,6 +1053,40 @@ std_logic\end_layout
\begin_layout Plain Layout
Valid synchronisation edge appeared (Recessive to Dominant)\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
tq_edge\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
in\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Time quanta edge\end_layout
\end_inset
</cell>
</row>
......
This diff is collapsed.
......@@ -324,7 +324,7 @@ Ports\end_layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="4" rows="112" version="3">
<lyxtabular columns="4" rows="113" version="3">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
......@@ -1137,6 +1137,40 @@ std_logic\end_layout
\begin_layout Plain Layout
Overload frame is being transmitted\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
is_sof\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
out\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Start of Frame\end_layout
\end_inset
</cell>
</row>
......
......@@ -131,6 +131,9 @@ entity bus_sampling is
-- Valid synchronisation edge appeared (Recessive to Dominant)
sync_edge :out std_logic;
-- Time quanta edge
tq_edge :in std_logic;
------------------------------------------------------------------------
-- CAN Core Interface
......@@ -299,9 +302,11 @@ begin
tx_data => tx_data_wbs, -- IN
rx_data => data_rx_synced, -- IN
prev_rx_sample => prev_sample, -- IN
tq_edge => tq_edge, -- IN
tx_edge => edge_tx_valid, -- OUT
rx_edge => edge_rx_valid -- OUT
rx_edge => edge_rx_valid, -- OUT
sync_edge => sync_edge -- OUT
);
......@@ -450,15 +455,12 @@ begin
);
-- Output data propagation - Pipe directly - no delay
can_tx <= tx_data_wbs;
can_tx <= tx_data_wbs;
-- RX Data for bit destuffing - Output of re-synchroniser.
rx_data_wbs <= data_rx_synced;
-- As synchroniation edge, valid edge on RX Data is selected!
sync_edge <= edge_rx_valid;
rx_data_wbs <= data_rx_synced;
-- Registers to output propagation
sample_sec <= sample_sec_i;
sample_sec <= sample_sec_i;
end architecture;
\ No newline at end of file
......@@ -107,6 +107,9 @@ entity data_edge_detector is
-- RX Data value from previous Sample point.
prev_rx_sample :in std_logic;
-- Time quanta edge
tq_edge :in std_logic;
------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------
......@@ -114,7 +117,10 @@ entity data_edge_detector is
tx_edge :out std_logic;
-- Edge detected on RX Data
rx_edge :out std_logic
rx_edge :out std_logic;
-- Synchronisation edge
sync_edge :out std_logic
);
end entity;
......@@ -124,6 +130,7 @@ architecture rtl of data_edge_detector is
-- Previous values on rx_data, tx_data inputs to detect edge
signal rx_data_prev : std_logic;
signal tx_data_prev : std_logic;
signal rx_data_sync_prev : std_logic;
-- Immediate edges on tx_data, rx_data (not yet finally valid)
signal rx_edge_immediate : std_logic;
......@@ -144,10 +151,15 @@ begin
if (res_n = G_RESET_POLARITY) then
rx_data_prev <= RECESSIVE;
tx_data_prev <= RECESSIVE;
rx_data_sync_prev <= RECESSIVE;
elsif (rising_edge(clk_sys)) then
rx_data_prev <= rx_data;
tx_data_prev <= tx_data;
end if;
if (tq_edge = '1') then
rx_data_sync_prev <= rx_data;
end if;
end if;
end process;
......@@ -159,7 +171,7 @@ begin
'0';
tx_edge_immediate <= '1' when (tx_data_prev /= tx_data) else
'0';
'0';
----------------------------------------------------------------------------
......@@ -185,10 +197,27 @@ begin
else
'0';
----------------------------------------------------------------------------
-- Synchronisation edge:
-- 1. Edge on RX data, aligned with Time Quanta
-- 2. Recessive to Dominant
-- 3. Data sampled in previous Sample point are different from actual
-- rx_data immediately after edge!
-- 4. Aligned with time quanta!
----------------------------------------------------------------------------
sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and
(rx_data_sync_prev = RECESSIVE) and
(prev_rx_sample /= rx_data) and
(tq_edge = '1')
else
'0';
----------------------------------------------------------------------------
-- Internal signals to output propagation
----------------------------------------------------------------------------
rx_edge <= rx_edge_i;
tx_edge <= tx_edge_i;
end architecture;
\ No newline at end of file
......@@ -467,6 +467,9 @@ architecture rtl of can_top_level is
------------------------------------------------------------------------
-- Bit time FSM state
signal bt_fsm : t_bit_time;
-- Time quanta edge
signal tq_edge : std_logic;
begin
......@@ -867,7 +870,8 @@ begin
tx_trigger => tx_trigger, -- OUT
-- Status outputs
bt_fsm => bt_fsm -- OUT
bt_fsm => bt_fsm, -- OUT
tq_edge => tq_edge -- OUT
);
......@@ -900,6 +904,7 @@ begin
rx_trigger => rx_triggers(1), -- IN
tx_trigger => tx_trigger, -- IN
sync_edge => sync_edge, -- OUT
tq_edge => tq_edge, -- IN
-- CAN Core Interface
tx_data_wbs => tx_data_wbs, -- IN
......
......@@ -241,6 +241,9 @@ package can_components is
-- Valid synchronisation edge appeared (Recessive to Dominant)
sync_edge :out std_logic;
-- Time quanta edge
tq_edge :out std_logic;
------------------------------------------------------------------------
-- CAN Core Interface
......@@ -355,6 +358,9 @@ package can_components is
-- RX Data value from previous Sample point.
prev_rx_sample :in std_logic;
-- Time quanta edge
tq_edge :in std_logic;
------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------
......@@ -362,7 +368,10 @@ package can_components is
tx_edge :out std_logic;
-- Edge detected on RX Data
rx_edge :out std_logic
rx_edge :out std_logic;
-- Synchronisation edge
sync_edge :out std_logic
);
end component data_edge_detector;
......@@ -3461,7 +3470,10 @@ package can_components is
-----------------------------------------------------------------------
-- Bit Time FSM state
bt_fsm : out t_bit_time
bt_fsm : out t_bit_time;
-- Time quanta edge
tq_edge : out std_logic
);
end component;
......
......@@ -155,7 +155,10 @@ entity prescaler is
-- Status outputs
-----------------------------------------------------------------------
-- Bit Time FSM state
bt_fsm : out t_bit_time
bt_fsm : out t_bit_time;
-- Time quanta edge
tq_edge : out std_logic
);
end entity;
......@@ -226,7 +229,7 @@ architecture rtl of prescaler is
-- Time quanta edges
signal tq_edge_nbt : std_logic;
signal tq_edge_dbt : std_logic;
-- Sample trigger request (in sample point)
signal rx_trig_req : std_logic;
......@@ -468,6 +471,9 @@ begin
rx_triggers => rx_triggers, -- OUT
tx_trigger => tx_trigger -- OUT
);
tq_edge <= tq_edge_nbt when (sp_control = NOMINAL_SAMPLE) else
tq_edge_dbt;
-- <RELEASE_OFF>
---------------------------------------------------------------------------
......
......@@ -453,6 +453,10 @@ begin
--wait for 10 ns;
info("... ready .. let's begin");
-- Initialize TXT Buffer memories (not to have too many logs!)
CAN_init_txtb_mems(ID_1, mem_bus(1));
CAN_init_txtb_mems(ID_2, mem_bus(2));
--Execute the controllers configuration
CAN_turn_controller(true, ID_1, mem_bus(1));
CAN_turn_controller(true, ID_2, mem_bus(2));
......
......@@ -86,6 +86,7 @@ USE ieee.math_real.ALL;
USE work.randomLib.All;
use work.can_constants.all;
use work.drv_stat_pkg.all;
use work.can_config.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
......@@ -2078,6 +2079,20 @@ package CANtestLib is
constant skip_stuff_bits : in boolean := true
);
----------------------------------------------------------------------------
-- Initialize TXT Buffer memories
--
-- Arguments:
-- ID Index of CTU CAN FD Core instance.
-- mem_bus Avalon memory bus to execute the access on.
----------------------------------------------------------------------------
procedure CAN_init_txtb_mems(
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Component declarations
......@@ -4969,7 +4984,8 @@ package body CANtestLib is
address := TX_PRIORITY_ADR;
CAN_write(data, address, ID, mem_bus, BIT_16);
end procedure;
procedure CAN_read_error_code_capture(
variable err_capt : inout SW_error_capture;
constant ID : in natural range 0 to 15;
......@@ -5030,6 +5046,24 @@ package body CANtestLib is
end procedure;
procedure CAN_init_txtb_mems(
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
) is
variable address : std_logic_vector(11 downto 0);
variable data : std_logic_vector(31 downto 0):=
(OTHERS => '0');
begin
for i in 1 to C_TXT_BUFFER_COUNT loop
address := std_logic_vector(to_unsigned(
to_integer((unsigned(TXTB1_DATA_1_ADR)) * i), 12));
for j in 0 to 19 loop
CAN_write(data, address, ID, mem_bus);
address := std_logic_vector(unsigned(address) + 4);
end loop;
end loop;
end procedure;
end package body;
......
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