Commit bc448cae authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added shift reg with no preload. Added simple DFF wrapper.

Re-worked interrupt module to use explicit enable for
interrupt mask.
parent d412b32f
......@@ -83,9 +83,9 @@ package cmn_lib is
----------------------------------------------------------------------------
-- Shift register
-- Shift register with preload
----------------------------------------------------------------------------
component shift_reg is
component shift_reg_preload is
generic (
constant reset_polarity : std_logic;
constant reset_value : std_logic_vector;
......@@ -102,6 +102,27 @@ package cmn_lib is
signal reg_stat : out std_logic_vector(width - 1 downto 0);
signal output : out std_logic
);
end component shift_reg_preload;
----------------------------------------------------------------------------
-- Shift register
----------------------------------------------------------------------------
component shift_reg is
generic (
constant reset_polarity : std_logic;
constant reset_value : std_logic_vector;
constant width : natural;
constant shift_down : boolean
);
port (
signal clk : in std_logic;
signal res_n : in std_logic;
signal input : in std_logic;
signal enable : in std_logic;
signal reg_stat : out std_logic_vector(width - 1 downto 0);
signal output : out std_logic
);
end component shift_reg;
......@@ -116,5 +137,25 @@ package cmn_lib is
end component majority_decoder_3;
----------------------------------------------------------------------------
-- Simple DFF with configurable width with asynchronous reset.
----------------------------------------------------------------------------
component dff_arst is
generic (
constant reset_polarity : std_logic;
constant rst_val : std_logic
);
port (
signal arst : in std_logic;
signal clk : in std_logic;
signal input : in std_logic;
signal load : in std_logic;
signal output : out std_logic
);
end component dff_arst;
end package cmn_lib;
......@@ -287,6 +287,11 @@ architecture rtl of bus_sampling is
signal trv_meas_running : std_logic;
signal trv_meas_to_restart : std_logic;
-- Reset for shift registers. This is used instead of shift register with
-- preload to lower the resource usage! Resetting and preloading to the
-- same value can be merged into just resetting by OR of sources
signal shift_regs_res_n : std_logic;
begin
---------------------------------------------------------------------------
......@@ -472,6 +477,15 @@ begin
end process;
----------------------------------------------------------------------------
-- Reset for shift registers for secondary sampling point
----------------------------------------------------------------------------
shift_regs_res_n <= ACT_RESET when (res_n = ACT_RESET) or
(ssp_reset = '1')
else
not ACT_RESET;
----------------------------------------------------------------------------
-- Shift register for secondary sampling point. Normal sample point trigger
-- is shifted into shift register to generate delayed sampling point.
......@@ -485,11 +499,11 @@ begin
)
port map(
clk => clk_sys,
res_n => res_n,
res_n => shift_regs_res_n,
input => sample_dbt,
preload => ssp_reset,
preload_val => SSP_SHIFT_RST_VAL,
--preload => ssp_reset,
--preload_val => SSP_SHIFT_RST_VAL,
enable => '1',
reg_stat => sample_sec_shift,
......@@ -509,12 +523,12 @@ begin
)
port map(
clk => clk_sys,
res_n => res_n,
res_n => shift_regs_res_n,
input => data_tx,
preload => ssp_reset,
preload_val => TX_DATA_SHIFT_RST_VAL,
--preload => ssp_reset,
--preload_val => TX_DATA_SHIFT_RST_VAL,
enable => '1',
reg_stat => tx_data_shift,
......@@ -575,7 +589,7 @@ begin
-- desired then majority out of whole shift register is selected as sampled
-- value!
----------------------------------------------------------------------------
trs_shift_reg_comp : shift_reg
trs_shift_reg_comp : shift_reg_preload
generic map(
reset_polarity => ACT_RESET,
reset_value => "000",
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Flip-flop with asynchronous reset template. Single bit version
--------------------------------------------------------------------------------
-- Revision History:
-- 20.12.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
entity dff_arst is
generic (
constant reset_polarity : std_logic;
constant rst_val : std_logic
);
port (
signal arst : in std_logic;
signal clk : in std_logic;
signal input : in std_logic;
signal load : in std_logic;
signal output : out std_logic
);
end dff_arst;
architecture rtl of dff_arst is
begin
-- DFF process
dff_proc : process (clk, arst)
begin
if (arst = reset_polarity) then
output <= rst_val;
elsif (rising_edge(clk)) then
if (load = '1') then
output <= input;
end if;
end if;
end process;
end rtl;
......@@ -72,12 +72,6 @@ entity shift_reg is
-- Input to a shift register
signal input : in std_logic;
-- Preload signal
signal preload : in std_logic;
-- Value to be preloaded to the shift register
signal preload_val : in std_logic_vector(width - 1 downto 0);
-- Enable for shift register. When enabled, shifted each clock, when
-- disabled, register keeps its state.
signal enable : in std_logic;
......@@ -122,9 +116,7 @@ begin
shift_regs <= reset_value;
elsif (rising_edge(clk)) then
if (preload = '1') then
shift_regs <= preload_val;
elsif (enable = '1') then
if (enable = '1') then
shift_regs <= next_shift_reg_val;
end if;
end if;
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Generic shift register.
--------------------------------------------------------------------------------
-- Revision History:
-- 23.11.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
entity shift_reg_preload is
generic (
constant reset_polarity : std_logic;
constant reset_value : std_logic_vector;
constant width : natural;
-- When 'true', values are shifted from highest index and output taken
-- from lowest index. When 'false' value are shifter from lowest index
-- and output taken from highest index.
constant shift_down : boolean
);
port (
-----------------------------------------------------------------------
-- Clock and reset
-----------------------------------------------------------------------
signal clk : in std_logic;
signal res_n : in std_logic;
-- Input to a shift register
signal input : in std_logic;
-- Preload signal
signal preload : in std_logic;
-- Value to be preloaded to the shift register
signal preload_val : in std_logic_vector(width - 1 downto 0);
-- Enable for shift register. When enabled, shifted each clock, when
-- disabled, register keeps its state.
signal enable : in std_logic;
-- Register parallel output
signal reg_stat : out std_logic_vector(width - 1 downto 0);
-- Register output
signal output : out std_logic
);
end shift_reg_preload;
architecture rtl of shift_reg_preload is
-- Internal shift register DFFs
signal shift_regs : std_logic_vector(width - 1 downto 0);
-- Combinational next value of shift register
signal next_shift_reg_val : std_logic_vector(width - 1 downto 0);
begin
---------------------------------------------------------------------------
-- Calculation of next shift register value
---------------------------------------------------------------------------
shift_down_gen : if (shift_down) generate
next_shift_reg_val <= input & shift_regs(width - 1 downto 1);
output <= shift_regs(0);
end generate shift_down_gen;
shift_up_gen : if (not shift_down) generate
next_shift_reg_val <= shift_regs(width - 2 downto 0) & input;
output <= shift_regs(width - 1);
end generate shift_up_gen;
---------------------------------------------------------------------------
-- Implementation of a shift register
---------------------------------------------------------------------------
shift_down_proc : process (clk)
begin
if (res_n = reset_polarity) then
shift_regs <= reset_value;
elsif (rising_edge(clk)) then
if (preload = '1') then
shift_regs <= preload_val;
elsif (enable = '1') then
shift_regs <= next_shift_reg_val;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Propagation of shift register to the outputs
---------------------------------------------------------------------------
reg_stat <= shift_regs;
---------------------------------------------------------------------------
-- Assertion for correct length of reset value
---------------------------------------------------------------------------
assert (reset_value'length = width) report "Invalid length of shift " &
"register reset value" severity error;
end rtl;
......@@ -57,6 +57,8 @@
--------------------------------------------------------------------------------
-- Revision History:
-- 11.12.2018 Created file
-- 20.12.2018 Re-worked Interrupt mask and Interrupt enable for better
-- synthesis.
--------------------------------------------------------------------------------
Library ieee;
......@@ -104,9 +106,14 @@ end entity;
architecture rtl of int_module is
-- Internal values
signal int_mask_i : std_logic;
signal int_ena_i : std_logic;
-- Interrupt mask handling signals
signal int_mask_load : std_logic;
signal int_mask_next : std_logic;
begin
------------------------------------------------------------------------
......@@ -162,6 +169,7 @@ begin
------------------------------------------------------------------------
-- Interrupt mask
------------------------------------------------------------------------
int_mask_proc : process(res_n, clk_sys)
begin
if (res_n = reset_polarity) then
......@@ -169,18 +177,19 @@ begin
elsif rising_edge(clk_sys) then
-- Setting Interrupt Mask
if (int_mask_set = '1') then
int_mask_i <= '1';
-- Clearing Interrupt Mask
elsif (int_mask_clear = '1') then
int_mask_i <= '0';
-- Setting / Clearing Interrupt Mask
if (int_mask_load = '1') then
int_mask_i <= int_mask_next;
end if;
end if;
end process;
int_mask_load <= int_mask_set or int_mask_clear;
int_mask_next <= '1' when (int_mask_set = '1')
else
'0';
------------------------------------------------------------------------
-- Interrupt Enable
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment