test: Add ERR_CAPT in EOF feature test.

test/feature/err_capt_eof_feature_tb.vhd

+--------------------------------------------------------------------------------
+-- 
+-- CTU CAN FD IP Core
+-- Copyright (C) 2015-2018
+-- 
+-- Authors:
+--     Ondrej Ille <ondrej.ille@gmail.com>
+--     Martin Jerabek <martin.jerabek01@gmail.com>
+-- 
+-- Project advisors: 
+-- 	Jiri Novak <jnovak@fel.cvut.cz>
+-- 	Pavel Pisa <pisa@cmp.felk.cvut.cz>
+-- 
+-- Department of Measurement         (http://meas.fel.cvut.cz/)
+-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
+-- Czech Technical University        (http://www.cvut.cz/)
+-- 
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this VHDL component and associated documentation files (the "Component"),
+-- to deal in the Component without restriction, including without limitation
+-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
+-- and/or sell copies of the Component, and to permit persons to whom the
+-- Component is furnished to do so, subject to the following conditions:
+-- 
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Component.
+-- 
+-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
+-- IN THE COMPONENT.
+-- 
+-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
+-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
+-- protocol license from Bosch.
+-- 
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+-- @TestInfoStart
+--
+-- @Purpose:
+--  ERR_CAPT[ERR_POS] = ERC_POS_EOF. Error code capture in End of frame feature
+--  test.
+--
+-- @Verifies:
+--  @1. Detection of Form error in End of frame field. Value of ERR_CAPT when
+--      Form Error should have been detected in EOF field.
+--
+-- @Test sequence:
+--  @1. Check that ERR_CAPT contains no error (post reset).
+--  @2. Generate CAN frame and send it by Node 1. Wait until End of frame field
+--      of Node 1 and wait for random number of bits (between 0 and 4). Force
+--      bus level dominant and wait until sample point. Check that Error frame
+--      is being transmitted and check value of ERR_CAPT.
+--
+-- @TestInfoEnd
+--------------------------------------------------------------------------------
+-- Revision History:
+--    12.01.2020   Created file
+--------------------------------------------------------------------------------
+
+context work.ctu_can_synth_context;
+context work.ctu_can_test_context;
+
+use lib.pkg_feature_exec_dispath.all;
+
+package err_capt_eof_feature is
+    procedure err_capt_eof_feature_exec(
+        signal      so              : out    feature_signal_outputs_t;
+        signal      rand_ctr        : inout  natural range 0 to RAND_POOL_SIZE;
+        signal      iout            : in     instance_outputs_arr_t;
+        signal      mem_bus         : inout  mem_bus_arr_t;
+        signal      bus_level       : in     std_logic
+    );
+end package;
+
+
+package body err_capt_eof_feature is
+    procedure err_capt_eof_feature_exec(
+        signal      so              : out    feature_signal_outputs_t;
+        signal      rand_ctr        : inout  natural range 0 to RAND_POOL_SIZE;
+        signal      iout            : in     instance_outputs_arr_t;
+        signal      mem_bus         : inout  mem_bus_arr_t;
+        signal      bus_level       : in     std_logic
+    ) is
+        variable ID_1               :     natural := 1;
+        variable ID_2               :     natural := 2;
+        
+        -- Generated frames
+        variable frame_1            :     SW_CAN_frame_type;
+
+        -- Node status
+        variable stat_1             :     SW_status;
+        variable stat_2             :     SW_status;
+
+        variable pc_dbg             :     SW_PC_Debug;    
+
+        variable frame_sent         :     boolean;
+        
+        variable err_capt           :     SW_error_capture;
+        variable mode_2             :     SW_mode := SW_mode_rst_val;
+        variable wait_time          :     natural;
+    begin
+
+        -----------------------------------------------------------------------
+        -- @1. Check that ERR_CAPT contains no error (post reset).
+        -----------------------------------------------------------------------
+        info("Step 1");
+        
+        CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
+        check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!");
+        
+        -----------------------------------------------------------------------        
+        -- @2. Generate CAN frame and send it by Node 1. Wait until End of
+        --     frame field of Node 1 and wait for random number of bits
+        --     (between 0 and 4). Force bus level dominant and wait until
+        --     sample point. Check that Error frame is being transmitted and
+        --     check value of ERR_CAPT.
+        -----------------------------------------------------------------------
+        info("Step 2");
+        
+        CAN_generate_frame(rand_ctr, frame_1);
+        CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent);
+        
+        CAN_wait_pc_state(pc_deb_eof, ID_1, mem_bus(1));
+        wait for 30 ns;
+
+        rand_int_v(rand_ctr, 4, wait_time);
+        info("waiting for:" & integer'image(wait_time) & " bits!");
+        for i in 1 to wait_time loop
+            CAN_wait_sync_seg(iout(1).stat_bus);
+        end loop;
+
+        force_bus_level(DOMINANT, so.bl_force, so.bl_inject);
+        CAN_wait_sample_point(iout(1).stat_bus);
+        wait for 20 ns;
+        release_bus_level(so.bl_force);
+
+        CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
+        check(err_capt.err_type = can_err_form, "Form error detected!");
+        check(err_capt.err_pos = err_pos_eof,
+            "Error detected in EOF field!");
+
+        CAN_wait_bus_idle(ID_1, mem_bus(1));
+        CAN_wait_bus_idle(ID_2, mem_bus(2));
+
+        wait for 100 ns;
+
+  end procedure;
+
+end package body;

test/tests_fast.yml

@@ -70,6 +70,7 @@ feature:
         err_capt_ctrl_bit:
         err_capt_ctrl_form:
         err_capt_data_bit:
+        err_capt_eof:
         err_capt_sof:
         err_norm_fd:
         error_rules_a:

test/tests_nightly.yml

@@ -101,6 +101,7 @@ feature:
         err_capt_ctrl_bit:
         err_capt_ctrl_form:
         err_capt_data_bit:
+        err_capt_eof:
         err_capt_sof:
         err_norm_fd:
             iterations: 5