Commit ba912972 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

SRC REGISTERS Fixed reset.

Fixed reset of memory registers module. Soft reset by MODE[RST]
should also reset content of memory register. Added driver
of res_out to also reset generated register components.
parent 93cda23a
Pipeline #5714 passed with stages
in 12 minutes and 7 seconds
......@@ -319,6 +319,8 @@ architecture rtl of memory_registers is
signal error_state : error_state_type;
signal OP_State : oper_mode_type;
-- Internal value of output reset. This is combined res_n and MODE[RST]
signal res_out_i : std_logic;
---------------------------------------------------------------------------
--
......@@ -455,7 +457,7 @@ begin
)
port map(
clk_sys => clk_sys,
res_n => res_n,
res_n => res_out_i,
address => adress,
w_data => data_in,
r_data => control_registers_rdata,
......@@ -485,7 +487,7 @@ begin
)
port map(
clk_sys => clk_sys,
res_n => res_n,
res_n => res_out_i,
address => adress,
w_data => data_in,
r_data => event_logger_rdata,
......@@ -517,10 +519,10 @@ begin
-- Reset propagation to output
-- Note: this works only for reset active in logic zero
----------------------------------------------------------------------------
res_out <= ACT_RESET when (res_n = ACT_RESET) else
ACT_RESET when (control_registers_out.mode(RST_IND) = '1') else
(not ACT_RESET);
res_out_i <= ACT_RESET when (res_n = ACT_RESET) else
ACT_RESET when (control_registers_out.mode(RST_IND) = '1') else
(not ACT_RESET);
res_out <= res_out_i;
----------------------------------------------------------------------------
-- Extract Protocol control state from Status Bus
......
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