Commit b8566675 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch 'resource_optimizations' into 'master'

Resource optimizations

See merge request illeondr/CAN_FD_IP_Core!10
parents 77f34353 d11c02ae
......@@ -1376,7 +1376,7 @@ status open
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="4">
<lyxtabular version="3" rows="10" columns="4">
<features tabularvalignment="middle">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
......@@ -1723,6 +1723,44 @@ true
Core should support Range Identifier Filter
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tx_time_sup
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
boolean
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
true
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Core should supprt frame transmisison at exact time
\end_layout
\end_inset
</cell>
</row>
......@@ -19615,7 +19653,28 @@ TX Arbitrator circuit covers the functionality of frame selection between
than value in TX_DATA_2 and TX_DATA_3 words of the buffer.
Thus the Frame is only selected at the moment when external timestamp has
elapsed the reuqired transmission time.
The circuit combinationally propagates the metadata about the frame (Frame
Support of this behaviour is configurable via
\begin_inset Quotes eld
\end_inset
tx_time_sup
\begin_inset Quotes erd
\end_inset
generic.
If set to
\begin_inset Quotes eld
\end_inset
false
\begin_inset Quotes erd
\end_inset
frame is transmitted as soon as inserted to the TXT Buffer.
\end_layout
\begin_layout Plain Layout
The circuit combinationally propagates the metadata about the frame (Frame
format, DLC, Frame type, Identifier) on the output.
The frame is selected combinationally and once the CAN Core acknowledges
that metadata were stored in TranBuffer, it waits until the frame transmission
......@@ -37888,12 +37947,30 @@ BRS Bit-rate shift.
\end_layout
\begin_layout Description
TS_VAL An External timestamp value when controller should attempt to start
frame transmission.
TS_VAL These word have meaning only if
\begin_inset Quotes eld
\end_inset
tx_time_sup=true
\begin_inset Quotes erd
\end_inset
.
An External timestamp value when controller should attempt to start frame
transmission.
If bus is Idle then transmission will start within next bit time.
Otherwise, it will start as soon as bus is idle.
If the frame should be transmitted immediately all zeroes must be written
into these two registers.
If
\begin_inset Quotes eld
\end_inset
tx_time_sup=false
\begin_inset Quotes erd
\end_inset
then frame is transmitted as soon as bus is idle.
\end_layout
\begin_layout Description
......@@ -1376,7 +1376,7 @@ status open
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="4">
<lyxtabular version="3" rows="10" columns="4">
<features tabularvalignment="middle">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
......@@ -1723,6 +1723,44 @@ true
Core should support Range Identifier Filter
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tx_time_sup
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
boolean
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
true
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Core should supprt frame transmisison at exact time
\end_layout
\end_inset
</cell>
</row>
......@@ -19615,7 +19653,28 @@ TX Arbitrator circuit covers the functionality of frame selection between
than value in TX_DATA_2 and TX_DATA_3 words of the buffer.
Thus the Frame is only selected at the moment when external timestamp has
elapsed the reuqired transmission time.
The circuit combinationally propagates the metadata about the frame (Frame
Support of this behaviour is configurable via
\begin_inset Quotes eld
\end_inset
tx_time_sup
\begin_inset Quotes erd
\end_inset
generic.
If set to
\begin_inset Quotes eld
\end_inset
false
\begin_inset Quotes erd
\end_inset
frame is transmitted as soon as inserted to the TXT Buffer.
\end_layout
\begin_layout Plain Layout
The circuit combinationally propagates the metadata about the frame (Frame
format, DLC, Frame type, Identifier) on the output.
The frame is selected combinationally and once the CAN Core acknowledges
that metadata were stored in TranBuffer, it waits until the frame transmission
......@@ -37888,8 +37947,17 @@ BRS Bit-rate shift.
\end_layout
\begin_layout Description
TS_VAL An External timestamp value when controller should attempt to start
frame transmission.
TS_VAL These word have meaning only if
\begin_inset Quotes eld
\end_inset
tx_time_sup=true
\begin_inset Quotes erd
\end_inset
.
An External timestamp value when controller should attempt to start frame
transmission.
If bus is Idle then transmission will start within next bit time.
Otherwise, it will start as soon as bus is idle.
If the frame should be transmitted immediately all zeroes must be written
......@@ -44994,6 +45062,8 @@ TX_Arbitrator
\end_layout
\begin_layout Standard
\color red
TX_Arbitrator testbench independently generates inputs to the TX Arbitrator
in input_gen process.
Since the whole circuit is only combinational it provides immediate (in
......@@ -45026,6 +45096,8 @@ TX_Buffer
\end_layout
\begin_layout Standard
\color red
TXT buffer unit test instantiates two DUTs with IDs 1 and 2 as in CAN FD
IP.
The difference is that one TXT buffer is set to support FD frames, the
......@@ -175,29 +175,29 @@ architecture rtl of messageFilter is
begin
--Driving signal aliases
drv_filter_A_mask <= drv_bus(DRV_FILTER_A_MASK_HIGH downto
DRV_FILTER_A_MASK_LOW);
DRV_FILTER_A_MASK_LOW);
drv_filter_A_ctrl <= drv_bus(DRV_FILTER_A_CTRL_HIGH downto
DRV_FILTER_A_CTRL_LOW);
DRV_FILTER_A_CTRL_LOW);
drv_filter_A_bits <= drv_bus(DRV_FILTER_A_BITS_HIGH downto
DRV_FILTER_A_BITS_LOW);
DRV_FILTER_A_BITS_LOW);
drv_filter_B_mask <= drv_bus(DRV_FILTER_B_MASK_HIGH downto
DRV_FILTER_B_MASK_LOW);
DRV_FILTER_B_MASK_LOW);
drv_filter_B_ctrl <= drv_bus(DRV_FILTER_B_CTRL_HIGH downto
DRV_FILTER_B_CTRL_LOW);
DRV_FILTER_B_CTRL_LOW);
drv_filter_B_bits <= drv_bus(DRV_FILTER_B_BITS_HIGH downto
DRV_FILTER_B_BITS_LOW);
DRV_FILTER_B_BITS_LOW);
drv_filter_C_mask <= drv_bus(DRV_FILTER_C_MASK_HIGH downto
DRV_FILTER_C_MASK_LOW);
DRV_FILTER_C_MASK_LOW);
drv_filter_C_ctrl <= drv_bus(DRV_FILTER_C_CTRL_HIGH downto
DRV_FILTER_C_CTRL_LOW);
DRV_FILTER_C_CTRL_LOW);
drv_filter_C_bits <= drv_bus(DRV_FILTER_C_BITS_HIGH downto
DRV_FILTER_C_BITS_LOW);
DRV_FILTER_C_BITS_LOW);
drv_filter_ran_ctrl <= drv_bus(DRV_FILTER_RAN_CTRL_HIGH downto
DRV_FILTER_RAN_CTRL_LOW);
DRV_FILTER_RAN_CTRL_LOW);
drv_filter_ran_lo_th <= drv_bus(DRV_FILTER_RAN_LO_TH_HIGH downto
DRV_FILTER_RAN_LO_TH_LOW);
DRV_FILTER_RAN_LO_TH_LOW);
drv_filter_ran_hi_th <= drv_bus(DRV_FILTER_RAN_HI_TH_HIGH downto
DRV_FILTER_RAN_HI_TH_LOW);
DRV_FILTER_RAN_HI_TH_LOW);
drv_filters_ena <= drv_bus(DRV_FILTERS_ENA_INDEX);
--Input frame type internal signal
......@@ -279,7 +279,7 @@ begin
int_filter_ran_valid <= '1' when (--Identifier matches the range set
(rec_ident_dec
<=
to_integer(unsigned(drv_filter_ran_hi_th)))
to_integer(unsigned(drv_filter_ran_hi_th)))
AND
(rec_ident_dec
>=
......
......@@ -91,10 +91,10 @@ use work.CANconstants.all;
entity rxBuffer is
GENERIC(
--Maximal number of 32 bit words to store (Minimal value=16, one 64 bytes
--message length) Only 2^k are allowed as buff_size. Memory adressing is
--in modular arithmetic, synthesis of modulo by number other than 2^k is
-- not supported!!!
--Maximal number of 32 bit words to store (Minimal value=16, one 64 bytes
--message length) Only 2^k are allowed as buff_size. Memory adressing is
--in modular arithmetic, synthesis of modulo by number other than 2^k is
-- not supported!!!
buff_size :natural range 4 to 512 :=32
);
PORT(
......@@ -206,7 +206,7 @@ entity rxBuffer is
constant data_width :natural := 32; --Word data width
type rx_memory is array(0 to buff_size-1) of
std_logic_vector(data_width-1 downto 0); --Memory type
std_logic_vector(data_width-1 downto 0); --Memory type
--Memory declaration inferred in SRAM
signal memory :rx_memory;
......@@ -267,10 +267,10 @@ begin
-- Address for the Receive data RAM in the CAN Core! Comparator is temporary
-- before the data order will be reversed!
rec_dram_addr <= 18-copy_counter when (copy_counter>2
and
copy_counter<19)
else
0;
and
copy_counter<19)
else
0;
------------------------------------------------------------------------------
--Storing data from CANCore and loading data into reading buffer
......@@ -392,11 +392,11 @@ begin
--Writing Frame format Word
rx_message_disc <= '0';
memory(write_pointer) <= "000000000000000000000"&
rec_esi&rec_brs&
'1'&rec_frame_type_in&
rec_ident_type_in&
rec_is_rtr&
'0'&rec_dlc_in;
rec_esi&rec_brs&
'1'&rec_frame_type_in&
rec_ident_type_in&
rec_is_rtr&
'0'&rec_dlc_in;
memory_valid(write_pointer) <= '1';
--Increasing write pointer
......@@ -487,7 +487,7 @@ begin
end if;
rx_mem_free <= std_logic_vector(
to_unsigned(mem_free,8));
to_unsigned(mem_free,8));
--Assigning output whenever memory is full
if (mem_free=0) then
......@@ -505,7 +505,7 @@ begin
--Propagating message count to output
rx_message_count <= std_logic_vector(
to_unsigned(message_count,8));
to_unsigned(message_count,8));
end if;
end process memory_acess;
......
......@@ -46,7 +46,8 @@ use work.ID_transfer.all;
-- Buffer to erase. Output data word is selected based on stored
-- value of "mess_src" from the time of decision between TXT1 and
-- TXT2 buffer.
--
-- 10.12.2017 Added "tx_time_sup" to enable/disable transmission at given
-- time and save some LUTs.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
......@@ -59,7 +60,10 @@ use work.ID_transfer.all;
-- equal and then message with lower identifier is selected!
--------------------------------------------------------------------------------
entity txArbitrator is
entity txArbitrator is
generic(
tx_time_sup : boolean := true
);
port(
------------------------
-- Clock and reset
......@@ -228,9 +232,17 @@ begin
ident2 <= txt2buf_info_in(TXT_IDW_HIGH-3 downto TXT_IDW_LOW);
--Comparator methods for 64 bit vectors
mt1_lt_mt2 <= less_than(mess_time1,mess_time2);
mt1_lt_ts <= less_than(mess_time1,timestamp);
mt2_lt_ts <= less_than(mess_time2,timestamp);
tx_gen_true:if (tx_time_sup=true) generate
mt1_lt_mt2 <= less_than(mess_time1,mess_time2);
mt1_lt_ts <= less_than(mess_time1,timestamp);
mt2_lt_ts <= less_than(mess_time2,timestamp);
end generate;
tx_gen_false:if (tx_time_sup=false) generate
mt1_lt_mt2 <= true;
mt1_lt_ts <= true;
mt2_lt_ts <= true;
end generate;
------------------------------------------------------------------------------
--Message can be transmitted when transmitt timestamp is lower than the actual
......@@ -297,9 +309,9 @@ begin
--at least one of the frames is valid
------------------------------------------------------------------------------
tran_frame_valid_out <= '1' when (ts_valid="10" or
ts_valid="01" or
ts_valid="11")
else
ts_valid="01" or
ts_valid="11")
else
'0';
------------------------------------------------------------------------------
......
......@@ -76,9 +76,9 @@ USE WORK.CANconstants.ALL;
entity busSync is
GENERIC (
--Whenever Synchronisation chain should be used for sampled data from the
--bus. Turn off only when Synthetizer puts synchronisation chain automa-
--tically on the output pins! Otherwise metastability issues will occur!
--Whenever Synchronisation chain should be used for sampled data from the
--bus. Turn off only when Synthetizer puts synchronisation chain automa-
--tically on the output pins! Otherwise metastability issues will occur!
use_Sync:boolean:=false
);
PORT(
......
......@@ -31,9 +31,9 @@ USE WORK.CANconstants.ALL;
-- June 2015 Version 1 of circuit
-- July 2015 Version 2 and 3 of circuit
-- 19.12.2015 Added minimal information processing time protection. It is no
-- longer possible to shorten PH2 segment less than 4 clock cycles.
-- longer possible to shorten PH2 segment less than 4 clock cycles.
-- No sampling signals are left out in this case!
--
-- 14.6.2016 1.Added reset state into the bit time FSM. As long as reset is
-- active bt_FSM is kept in reset. First clock cyle it comes out
-- reset sync is set. This removes the error that Sync sequence
......@@ -328,7 +328,7 @@ begin
--Internal aliases
tq_dur <= to_integer(unsigned(drv_tq_nbt))
when (sp_control=NOMINAL_SAMPLE) else
when (sp_control=NOMINAL_SAMPLE) else
to_integer(unsigned(drv_tq_dbt));
......@@ -502,7 +502,7 @@ begin
ph2_real<=1;
end if;
else
--This causes finish of ph2 in next time quantum
--This causes finish of ph2 in next time quantum
ph2_real<=bt_counter;
end if;
end if;
......@@ -520,7 +520,7 @@ begin
--So we shorten PH2 only to its minimal possible length. The
--length is dependent on time quantum duration
if(tq_dbt=1)then --Presc=1
--This is only case not according to specification
--This is only case not according to specification
ph2_real<=4;
elsif (tq_dbt=2) then --Presc=2
ph2_real<=2;
......@@ -541,8 +541,8 @@ begin
--form positive resynchronisation. Also when dominant bit was just
--send on the bus, no positive resynchronization is performed
elsif((data_tx=RECESSIVE)
and
(not(OP_State=transciever and sp_control=SECONDARY_SAMPLE)))
and
(not(OP_State=transciever and sp_control=SECONDARY_SAMPLE)))
then
if(bt_FSM=prop)then
if(sp_control=NOMINAL_SAMPLE)then
......@@ -723,7 +723,10 @@ begin
FSM_Preset<='0';
elsif(hard_sync_valid='1' and FSM_Preset='0')then
hard_sync_valid<='0';
elsif(hard_sync_valid='0' and FSM_Preset='0' and FSM_Preset_2='0')then
elsif(hard_sync_valid='0' and
FSM_Preset='0' and
FSM_Preset_2='0')
then
--One cycle has to be between sync signal! Otherwise PC control
--wont be able to react on hard sync valid!
--Here sync signal is finally set!
......@@ -766,25 +769,25 @@ begin
sample_nbt_del_1_r<='0';
sample_dbt_del_1_r<='0';
elsif rising_edge(clk_sys)then
if(sync_nbt_r='1')then sync_nbt_del_1_r<='1';
else sync_nbt_del_1_r<='0';
if (sync_nbt_r='1') then sync_nbt_del_1_r<='1';
else sync_nbt_del_1_r<='0';
end if;
if(sync_dbt_r='1')then sync_dbt_del_1_r<='1';
else sync_dbt_del_1_r<='0';
if (sync_dbt_r='1') then sync_dbt_del_1_r<='1';
else sync_dbt_del_1_r<='0';
end if;
if(sample_nbt_r='1')then sample_nbt_del_1_r<='1';
else sample_nbt_del_1_r<='0';
if (sample_nbt_r='1') then sample_nbt_del_1_r<='1';
else sample_nbt_del_1_r<='0';
end if;
if(sample_dbt_r='1')then sample_dbt_del_1_r<='1';
else sample_dbt_del_1_r<='0';
if (sample_dbt_r='1') then sample_dbt_del_1_r<='1';
else sample_dbt_del_1_r<='0';
end if;
if(sample_nbt_del_1_r='1')then sample_nbt_del_2_r<='1';
else sample_nbt_del_2_r<='0';
if (sample_nbt_del_1_r='1') then sample_nbt_del_2_r<='1';
else sample_nbt_del_2_r<='0';
end if;
if(sample_dbt_del_1_r='1')then sample_dbt_del_2_r<='1';
else sample_dbt_del_2_r<='0';
if (sample_dbt_del_1_r='1') then sample_dbt_del_2_r<='1';
else sample_dbt_del_2_r<='0';
end if;
end if;
......
......@@ -4,7 +4,7 @@ USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
-------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
......@@ -29,28 +29,31 @@ use work.CANconstants.all;
-- Revision History:
--
-- June 2015 Created file
-- 28.5.2016 Starting polynomial changed for crc 17 and crc 21. Highest bit is now fixed in logic one
-- to be compliant with CAN ISO FD. It will be needed to implement both ways still since ISO
-- and non-ISO FD will be changable via configuration bit!
-- 4.6.2016 Added drv_is_fd to cover differencce in highest bit of crc17 and crc21 polynomial
-------------------------------------------------------------------------------------------------------------
-- 28.5.2016 Starting polynomial changed for crc 17 and crc 21. Highest bit
-- is now fixed in logic one to be compliant with CAN ISO FD. It
-- will be needed to implement both ways still since ISO and
-- non-ISO FD will be changable via configuration bit!
-- 4.6.2016 Added drv_is_fd to cover differencce in highest bit of crc17
-- and crc21 polynomial
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- CRC Checking for CAN flexible data Rate. Three CRC are calculated simultaneously. Serial Data input. ---
-- Operation starts with enable transition from 0 to 1. Valid input data has to be present then. --
-- Circuit processes the data on trig signal in logic 1. Circuit operation finishes when 1 to 0 transiti --
-- on on enable signal appears. The output CRC is valid then. CRC stays valid until following 0 to 1 ena --
-- ble transition. This also erases CRC registers.
-- CRC Checking for CAN flexible data Rate. Three CRC are calculated simulta-
-- neously. Serial Data input. Operation starts with enable transition from 0
-- to 1. Valid input data has to be present then. Circuit processes the data on
-- trig signal in logic 1. Circuit operation finishes when 1 to 0 transition on
-- enable signal appears. The output CRC is valid then. CRC stays valid until
-- following 0 to 1 enable transition. This also erases CRC registers.
--
-- Refer to CAN 2.0 or CAN FD Specification for CRC calculation algorythm --
----------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity canCRC is
generic(
constant crc15_pol : std_logic_vector(15 downto 0):=std_logic_vector'(X"C599");
constant crc17_pol : std_logic_vector(19 downto 0):=std_logic_vector'(X"3685B");
constant crc21_pol : std_logic_vector(23 downto 0):=std_logic_vector'(X"302899")
constant crc15_pol : std_logic_vector(15 downto 0):=x"C599";
constant crc17_pol : std_logic_vector(19 downto 0):=x"3685B";
constant crc21_pol : std_logic_vector(23 downto 0):=x"302899"
);
port(
----------
......@@ -65,8 +68,9 @@ entity canCRC is
signal res_n :in std_logic; --Asynchronous reset
signal enable :in std_logic;
--By transition from 0 to 1 on enable sampled on clk_sys rising edge (and with trig='1')
--operation is started. First bit of data already has to be on data_in input.
--By transition from 0 to 1 on enable sampled on clk_sys rising edge
--(and with trig='1') operation is started. First bit of data already has
--to be on data_in input.
--Circuit works as long as enable=1.
signal drv_bus :in std_logic_vector(1023 downto 0);
......@@ -86,8 +90,11 @@ entity canCRC is
signal crc17_reg : std_logic_vector(16 downto 0);
signal crc21_reg : std_logic_vector(20 downto 0);
signal start_reg : std_logic; --Holds previous value of enable input. Detects 0 to 1 transition
signal drv_fd_type : std_logic; --ISO CAN FD or NON ISO CAN FD Value
--Holds previous value of enable input. Detects 0 to 1 transition
signal start_reg : std_logic;
--ISO CAN FD or NON ISO CAN FD Value
signal drv_fd_type : std_logic;
end entity;
......@@ -206,7 +213,7 @@ begin
crc21_reg <= (OTHERS=>'0');
crc21_reg(20) <= '1';
crc21_nxt := '0';
elsif rising_edge(clk_sys)then --TODO think of optimization IF clocks are synthetized via AND gate!!!
elsif rising_edge(clk_sys)then
--Erase the CRC value at the begining of
--calculation
......
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
library ieee;
use IEEE.std_logic_1164.all;