Commit b789db02 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Reset DUT between each iteration to avoid flaky old

values causing mismatches in the first bit.
parent e0698eab
......@@ -667,9 +667,11 @@ begin
drv_ena <= '0';
wait until rising_edge(clk_sys) and (bt_FSM_out = reset and bt_fsm_mod = reset);
res_n <= '0';
wait for 100 ns;
res_n <= '1';
drv_ena <= '1';
wait for 1000 ns;
Markdown is supported
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment