Commit b491690d authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Turned out this pretty innocent delay was the root cause

of inconsistency in the design. If async change occured
during this time, then old priorities were used instead
of new ones!
parent d4606e46
Pipeline #2026 passed with stages
in 5 minutes and 55 seconds
......@@ -237,12 +237,6 @@ begin
apply_rand_seed(seed, 3, rand_ctr_1);
end if;
-- Additional delay to be sure that we catch HW command lock as real
-- TX Arbitrator does by combinational path!
--wait for 1 ns;
-- Choose random TXT Buffer
rand_real_v(rand_ctr_1, buf_index);
buf_index := buf_index * 3.0;
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