Commit b45519c4 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Reworked Data-brief.

parent 7db6025a
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\begin_body
\begin_layout Title
\begin_inset space ~
\end_inset
\begin_inset Newline newline
\end_inset
CAN FLEXIBLE DATA-RATE
\begin_inset Newline newline
\end_inset
IP CORE
\noindent
CAN FD DATA-RATE IP CORE
\begin_inset Newline newline
\end_inset
......@@ -101,7 +98,12 @@ IP CORE
PRODUCT BRIEF
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\begin_layout Email
martin.jerabek01@gmail.com, ondrej.ille@gmail.com
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......@@ -165,7 +168,7 @@ Czech Technical University in Prague
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Faculty of electrical engineering
Faculty of Electrical Engineering
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......@@ -185,7 +188,7 @@ Faculty of electrical engineering
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Department of measurement
Department of Measurement
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......@@ -199,48 +202,30 @@ Department of measurement
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Ondrej Ille
\noindent
Martin Jerabek, Ondrej Ille
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August 2016
September 2018
\end_layout
\begin_layout Section*
\noindent
Overview
\end_layout
\begin_layout Standard
\paragraph_spacing single
CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
1.0 and ISO CAN FD specification in single light-weight IP Core.
It is soft-core IP Core written in VHDL with only standard IEEE libraries
1.0 and ISO CAN FD specification in a light - weight IP Core.
It is a soft-core IP Core written in VHDL, with no vendor specific libraries
needed.
The main target of usage are FPGA applications and the core is available
as RTL.
The main target of usage are FPGA applications, and the core RTL is available
under MIT License in Gitlab repository of CTU FEE.
It is optimized for inference of native hardware blocks such as SRAM memories
and multipliers in DSP blocks.
Generic settings achieve a high level of flexibility before synthesis.
It is posible to balance the core between high amount of features and small
size.
\end_layout
\begin_layout Standard
The IP Core is accessed as memory mapped peripheria via Avalon bus.
Easy manipulation with the core is achieved by using hardware buffers for
CAN frames.
One FIFO like RX buffer is available and two TX buffers are available.
Timestamps can be captured for various events on the CAN bus.
Additionally transmission of CAN frames can be triggered by external timestamp.
Asynchronous access is supported via rich interrupt settings.
Three Bit filters and one Range filter is available on received frames.
\end_layout
\begin_layout Standard
The design is fully tested at RTL level as well as in real hardware with
Altera Cyclone IV FPGA series.
The automated test-framework in TCL is available within the core and it
provides an easy way of reproducing unit test, feature covering tests and
real bus simulation.
and DSP blocks.
Generic settings achieve high level of flexibility before synthesis.
\end_layout
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......@@ -251,8 +236,9 @@ The design is fully tested at RTL level as well as in real hardware with
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......@@ -355,86 +261,116 @@ status open
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\begin_layout Standard
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The IP Core is accessed as a slave memory mapped peripheria via Avalon bus
or APB.
Easy manipulation with the core is achieved by using hardware buffers for
CAN frames.
One FIFO RX buffer is available, and 4 TX buffers are available.
Timestamps can be captured for various events on the CAN bus and transmission
of CAN frames can be triggered by external timestamp.
Three Bit filters and one Range filter is available for HW filtration of
received CAN frames.
The Core was synthesized in Xilinx and Altera FPGAs with approximate maximal
operating frequency of 100 MHz.
\end_layout
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\paragraph_spacing single
CTU CAN FD also contains a Linux SocketCAN driver.
The design contains its own testing framework which is based on Vunit test
framework and simulated via GHDL or Modelsim.
At the moment the development team of CTU CAN FD is working on ISO conformance
testing to guarantee proper operation in commercial applications.
\end_layout
\begin_layout Section*
\noindent
Features
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\paragraph_spacing other 0.5
\noindent
CAN 2.0, CAN FD 1.0 and ISO CAN FD
\end_layout
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RTL VHDL (synthesis), TCL (testing)
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\noindent
RTL VHDL
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\noindent
Pre-synthesis configurable features
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Avalon memory bus
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Avalon compatible memory bus, APB
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Timestamping and transmission at given time
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Optional event and error logging
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Fault confinement state manipulation
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Transceiver delay measurement
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Size 6 000 - 11 000 LUTs
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\noindent
Size of 1700-2300 ALMs (Intel) , 2500 - 3300 LUTs (Xilinx)
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2 000 - 12 000 SRAM memory bits
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3 500 - 138 000 SRAM memory bits (Intel), 2.5 - 6 BRAMS (Xilinx)
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Synchronization output with time quantum
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Variety of interrupt sources
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Filtering of received frame
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Filtering of received frames
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Listen-only mode, Self-test mode,
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Acknowledge forbidden mode
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Listen-only mode, Self-test mode, Acknowledge forbidden mode
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Up to 14 Mbit in
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......@@ -443,16 +379,13 @@ Data
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bit-rate
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(with 100 Mhz Core clock)
Bit-Rate (with 100 MHz Core clock)
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Driver in C available
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\noindent
Linux SocketCAN driver available
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......
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CAN FLEXIBLE DATA-RATE IP CORE
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PRODUCT BRIEF v2.1
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Czech Technical University in Prague
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Martin Jerabek, Ondrej Ille
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Overview
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CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
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It is a soft-core IP Core written in VHDL, with no vendor specific libraries
needed.
The main target of usage are FPGA applications, and the core RTL is freely
available under MIT License in Gitlab repository of CTU FEE.
It is optimized for inference of native hardware blocks such as SRAM memories
and DSP blocks.
Generic settings achieve high level of flexibility before synthesis.
\end_layout
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\paragraph_spacing single
The IP Core is accessed as a slave memory mapped peripheria via Avalon bus
or APB.
Easy manipulation with the core is achieved by using hardware buffers for
CAN frames.
One FIFO RX buffer is available, and 4 TX buffers are available.
Timestamps can be captured for various events on the CAN bus and transmission
of CAN frames can be triggered by external timestamp.
Three Bit filters and one Range filter is available for HW filtration of
received CAN frames.