Commit b112aba6 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Added Vivado benchmark project to evaluate FPGA resources.

parent c9c528cf
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Apr 24 09:33:28 2018">
<section name="Project Information" visible="false">
<property name="ProjectID" value="151929edaff848b780e40a893552cd2f" type="ProjectID"/>
<property name="ProjectIteration" value="2" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="ReportTimingSummary" value="1" type="JavaHandler"/>
<property name="ResetLayout" value="1" type="JavaHandler"/>
<property name="RunImplementation" value="2" type="JavaHandler"/>
<property name="RunSchematic" value="3" type="JavaHandler"/>
<property name="RunSynthesis" value="1" type="JavaHandler"/>
<property name="ShowPowerEstimation" value="1" type="JavaHandler"/>
<property name="ShowView" value="1" type="JavaHandler"/>
<property name="ToolsSettings" value="1" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
<property name="ZoomIn" value="13" type="JavaHandler"/>
<property name="ZoomOut" value="7" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="4" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="12" type="GuiHandlerData"/>
<property name="ExpReportTreePanel_EXP_REPORT_TREE_TABLE" value="1" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="14" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="39" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="20" type="GuiHandlerData"/>
<property name="GraphicalView_NEXT" value="1" type="GuiHandlerData"/>
<property name="InstanceMenu_FLOORPLANNING" value="1" type="GuiHandlerData"/>
<property name="LogMonitor_MONITOR" value="3" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="3" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="6" type="GuiHandlerData"/>
<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="6" type="GuiHandlerData"/>
<property name="NetlistSchematicView_SHOW_CELLS_IN_THIS_SCHEMATIC" value="2" type="GuiHandlerData"/>
<property name="NetlistTreeView_NETLIST_TREE" value="8" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_IMPLEMENTATION" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_IN" value="14" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_OUT" value="8" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="2" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="3" type="GuiHandlerData"/>
<property name="PrimitivesMenu_HIGHLIGHT_LEAF_CELLS" value="1" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_GROUP" value="1" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="3" type="GuiHandlerData"/>
<property name="SchematicView_PREVIOUS" value="10" type="GuiHandlerData"/>
<property name="SelectMenu_HIGHLIGHT" value="1" type="GuiHandlerData"/>
<property name="SelectMenu_MARK" value="1" type="GuiHandlerData"/>
<property name="SettingsDialog_OPTIONS_TREE" value="1" type="GuiHandlerData"/>
<property name="SettingsDialog_PROJECT_TREE" value="5" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
<property name="SrcMenu_OPEN_SELECTED_SOURCE_FILES" value="1" type="GuiHandlerData"/>
<property name="XPowerSettingsDialog_CANCEL" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="5" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="3" type="TclMode"/>
</item>
</section>
</application>
</document>
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
</Runs>
#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
reset_param project.defaultXPMLibraries
open_checkpoint /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1/CAN_top_level.dcp
set_property webtalk.parent_dir /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/wt [current_project]
set_property parent.project_path /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.xpr [current_project]
set_property ip_output_repo /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force CAN_top_level_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file CAN_top_level_drc_opted.rpt -pb CAN_top_level_drc_opted.pb -rpx CAN_top_level_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
implement_debug_core
place_design
write_checkpoint -force CAN_top_level_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file CAN_top_level_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file CAN_top_level_utilization_placed.rpt -pb CAN_top_level_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CAN_top_level_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force CAN_top_level_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file CAN_top_level_drc_routed.rpt -pb CAN_top_level_drc_routed.pb -rpx CAN_top_level_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file CAN_top_level_methodology_drc_routed.rpt -pb CAN_top_level_methodology_drc_routed.pb -rpx CAN_top_level_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file CAN_top_level_power_routed.rpt -pb CAN_top_level_power_summary_routed.pb -rpx CAN_top_level_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file CAN_top_level_route_status.rpt -pb CAN_top_level_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CAN_top_level_timing_summary_routed.rpt -warn_on_violation -rpx CAN_top_level_timing_summary_routed.rpx"
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CAN_top_level_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CAN_top_level_clock_utilization_routed.rpt"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force CAN_top_level_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
| Date : Thu Apr 19 18:31:52 2018
| Host : ondrej-Aspire-V3-771 running 64-bit Ubuntu 16.04.4 LTS
| Command : report_drc -file CAN_top_level_drc_opted.rpt -pb CAN_top_level_drc_opted.pb -rpx CAN_top_level_drc_opted.rpx
| Design : CAN_top_level
| Device : xc7z007sclg225-2
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: checkpoint_CAN_top_level
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 25
+-----------+------------------+----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+------------------+----------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CHECK-3 | Warning | Report rule limit reached | 1 |
| IOCNT-1 | Warning | Number of IOs | 1 |
| REQP-1840 | Warning | RAMB18 async control check | 20 |
| ZPS7-1 | Warning | PS7 block required | 1 |
+-----------+------------------+----------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
161 out of 161 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: adress[23], adress[22], adress[21], adress[20], adress[19], adress[18], adress[17], adress[16], adress[11], adress[10], adress[9], adress[8], adress[7], adress[6], adress[5] (the first 15 of 33 listed).
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
161 out of 161 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: adress[23], adress[22], adress[21], adress[20], adress[19], adress[18], adress[17], adress[16], adress[11], adress[10], adress[9], adress[8], adress[7], adress[6], adress[5] (the first 15 of 33 listed).
Related violations: <none>
CHECK-3#1 Warning
Report rule limit reached
REQP-1840 rule limit reached: 20 violations have been found.
Related violations: <none>
IOCNT-1#1 Warning
Number of IOs
The design contains 161 unplaced I/O ports while the target device, xc7z007sclg225-2, has 54 remaining available user I/O pins. This DRC assumes that all ports which do not drive MGT pins should be placed on user I/O pins. To correct this issue:
1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary.
2. Check the top-level ports of the design to ensure the correct number of ports are specified.
3. Consider design changes to reduce the number of user I/O pins needed.
Related violations: <none>
REQP-1840#1 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[0][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#2 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[0][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#3 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[0][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#4 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[1][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#5 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[1][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#6 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[1][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#7 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[2][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#8 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[2][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#9 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[2][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#10 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[3][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#11 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[6] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[1]) which is driven by a register (reg_comp/txt_buf_prior_reg[3][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#12 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[7] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[2]) which is driven by a register (core_top_comp/PC_State_comp/txt_buf_ptr_r_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#13 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[7] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[2]) which is driven by a register (tx_arb_comp/tx_arb_fsm_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#14 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[7] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[2]) which is driven by a register (tx_arb_comp/tx_arb_fsm_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#15 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[8] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[3]) which is driven by a register (core_top_comp/PC_State_comp/txt_buf_ptr_r_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#16 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[8] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[3]) which is driven by a register (tx_arb_comp/tx_arb_fsm_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#17 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[8] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[3]) which is driven by a register (tx_arb_comp/tx_arb_fsm_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#18 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[9] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[4]) which is driven by a register (core_top_comp/PC_State_comp/txt_buf_ptr_r_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#19 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[9] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[4]) which is driven by a register (tx_arb_comp/tx_arb_fsm_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#20 Warning
RAMB18 async control check
The RAMB18E1 txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg has an input control pin txt_buf_comp_gen[0].txtBuffer_comp/txt_buffer_mem_reg/ADDRARDADDR[9] (net: txt_buf_comp_gen[0].txtBuffer_comp/ADDRARDADDR[4]) which is driven by a register (tx_arb_comp/tx_arb_fsm_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
ZPS7-1#1 Warning
PS7 block required
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
Related violations: <none>
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7z007sclg225-2" LaunchTime="1524155436">
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<File Type="BG-DRC" Name="CAN_top_level.drc"/>
<File Type="BG-BGN" Name="CAN_top_level.bgn"/>
<File Type="BITSTR-SYSDEF" Name="CAN_top_level.sysdef"/>
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
<File Type="BITSTR-LTX" Name="CAN_top_level.ltx"/>
<File Type="BITSTR-MMI" Name="CAN_top_level.mmi"/>
<File Type="BITSTR-BMM" Name="CAN_top_level_bd.bmm"/>
<File Type="BITSTR-NKY" Name="CAN_top_level.nky"/>
<File Type="BITSTR-RBT" Name="CAN_top_level.rbt"/>
<File Type="BITSTR-MSK" Name="CAN_top_level.msk"/>
<File Type="BG-BIN" Name="CAN_top_level.bin"/>
<File Type="BG-BIT" Name="CAN_top_level.bit"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="CAN_top_level_timing_summary_postroute_physopted.rpx"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="CAN_top_level_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="CAN_top_level_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="CAN_top_level_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="CAN_top_level_postroute_physopt.dcp"/>
<File Type="ROUTE-CLK" Name="CAN_top_level_clock_utilization_routed.rpt"/>
<File Type="ROUTE-SIMILARITY" Name="CAN_top_level_incremental_reuse_routed.rpt"/>
<File Type="ROUTE-TIMING-RPX" Name="CAN_top_level_timing_summary_routed.rpx"/>
<File Type="ROUTE-TIMING-PB" Name="CAN_top_level_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="CAN_top_level_timing_summary_routed.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="CAN_top_level_route_status.pb"/>
<File Type="ROUTE-STATUS" Name="CAN_top_level_route_status.rpt"/>
<File Type="ROUTE-PWR-RPX" Name="CAN_top_level_power_routed.rpx"/>
<File Type="ROUTE-PWR-SUM" Name="CAN_top_level_power_summary_routed.pb"/>
<File Type="PLACE-IO" Name="CAN_top_level_io_placed.rpt"/>
<File Type="RDI-RDI" Name="CAN_top_level.vdi"/>
<File Type="PWROPT-TIMING" Name="CAN_top_level_timing_summary_pwropted.rpt"/>
<File Type="PLACE-UTIL" Name="CAN_top_level_utilization_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="CAN_top_level_timing_summary_postplace_pwropted.rpt"/>
<File Type="OPT-TIMING" Name="CAN_top_level_timing_summary_opted.rpt"/>
<File Type="OPT-HWDEF" Name="CAN_top_level.hwdef"/>
<File Type="OPT-METHODOLOGY-DRC" Name="CAN_top_level_methodology_drc_opted.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="CAN_top_level_incremental_reuse_pre_placed.rpt"/>
<File Type="PLACE-DCP" Name="CAN_top_level_placed.dcp"/>
<File Type="PA-TCL" Name="CAN_top_level.tcl"/>
<File Type="PWROPT-DRC" Name="CAN_top_level_drc_pwropted.rpt"/>
<File Type="PWROPT-DCP" Name="CAN_top_level_pwropt.dcp"/>
<File Type="REPORTS-TCL" Name="CAN_top_level_reports.tcl"/>
<File Type="OPT-DCP" Name="CAN_top_level_opt.dcp"/>
<File Type="PLACE-CLK" Name="CAN_top_level_clock_utilization_placed.rpt"/>
<File Type="PA-DCP" Name="CAN_top_level.dcp"/>
<File Type="PLACE-TIMING" Name="CAN_top_level_timing_summary_placed.rpt"/>
<File Type="INIT-TIMING" Name="CAN_top_level_timing_summary_init.rpt"/>
<File Type="OPT-DRC" Name="CAN_top_level_drc_opted.rpt"/>
<File Type="PLACE-UTIL-PB" Name="CAN_top_level_utilization_placed.pb"/>
<File Type="PHYSOPT-TIMING" Name="CAN_top_level_timing_summary_physopted.rpt"/>
<File Type="PLACE-CTRL" Name="CAN_top_level_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="CAN_top_level_incremental_reuse_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="CAN_top_level_postplace_pwropt.dcp"/>
<File Type="PHYSOPT-DCP" Name="CAN_top_level_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="CAN_top_level_drc_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="CAN_top_level_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="CAN_top_level_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="CAN_top_level_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="CAN_top_level_drc_routed.rpt"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="CAN_top_level_methodology_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="CAN_top_level_drc_routed.pb"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="CAN_top_level_methodology_drc_routed.pb"/>
<File Type="ROUTE-DRC-RPX" Name="CAN_top_level_drc_routed.rpx"/>
<File Type="ROUTE-PWR" Name="CAN_top_level_power_routed.rpt"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="CAN_top_level_methodology_drc_routed.rpx"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../../src/Libraries/CAN_FD_frame_format.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Libraries/CAN_FD_register_map.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Libraries/CANconstants.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Libraries/CANcomponents.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Registers_Memory_Interface/canfd_registers.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Buffers_Message_Handling/rxBuffer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/ID_transfer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Buffers_Message_Handling/txArbitrator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Buffers_Message_Handling/messageFilter.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Interrupts/intManager.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/CAN_Core/operationControl.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/CAN_Core/protocolControl.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>