Merge branch '128-bus-off-time' into 'master'

Resolve "Bus off time"

Closes #128

See merge request illeondr/CAN_FD_IP_Core!127

doc/core/registerMap.lyx

@@ -4021,11 +4021,11 @@ Reserved\end_layout
 
 \end_inset
 </cell>
-<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
+<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
 \begin_inset Text
 
 \begin_layout Plain Layout
-Reserved\end_layout
+ERCRST\end_layout
 
 \end_inset
 </cell>
@@ -4099,7 +4099,7 @@ Reset value\end_layout
 \begin_inset Text
 
 \begin_layout Plain Layout
--\end_layout
+0\end_layout
 
 \end_inset
 </cell>
@@ -4151,6 +4151,9 @@ RRB Release Receive buffer. This command deletes all data from the Receive buffe
 \begin_layout Description
 CDO Clear data overrun flag. This command will clear data overrun flag on RX Buffer.
 \end_layout
+\begin_layout Description
+ERCRST Error counter reset. Issuing this command will erase TX, RX error counters after 128 conecutive ocurrences of 11 recessive bits. This command can be used as protocol compliant transition from Bus-off to Error Active. Upon completion, TX RX Error counters are erased and fault confinement state is set to Error Active.
+\end_layout
 \begin_layout Standard
 \begin_inset VSpace bigskip
 \end_inset

driver/ctu_can_fd_regs.h

@@ -143,7 +143,8 @@ union ctu_can_fd_mode_command_status_settings {
 		uint32_t at                      : 1;
 		uint32_t rrb                     : 1;
 		uint32_t cdo                     : 1;
-		uint32_t reserved_15_12          : 4;
+		uint32_t ercrst                  : 1;
+		uint32_t reserved_15_13          : 3;
   /* STATUS */
 		uint32_t rbs                     : 1;
 		uint32_t dos                     : 1;
@@ -173,7 +174,8 @@ union ctu_can_fd_mode_command_status_settings {
 		uint32_t tbs                     : 1;
 		uint32_t dos                     : 1;
 		uint32_t rbs                     : 1;
-		uint32_t reserved_15_12          : 4;
+		uint32_t reserved_15_13          : 3;
+		uint32_t ercrst                  : 1;
 		uint32_t cdo                     : 1;
 		uint32_t rrb                     : 1;
 		uint32_t at                      : 1;

spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml

@@ -298,6 +298,18 @@
 						</ipxact:resets>
 						<ipxact:bitWidth>1</ipxact:bitWidth>
 					</ipxact:field>
+					<ipxact:field>
+						<ipxact:name>ERCRST</ipxact:name>
+						<ipxact:displayName>ERCRST</ipxact:displayName>
+						<ipxact:description>Error counter reset. Issuing this command will erase TX, RX error counters after 128 conecutive ocurrences of 11 recessive bits. This command can be used as protocol compliant transition from Bus-off to Error Active. Upon completion, TX RX Error counters are erased and fault confinement state is set to Error Active.</ipxact:description>
+						<ipxact:bitOffset>4</ipxact:bitOffset>
+						<ipxact:resets>
+							<ipxact:reset>
+								<ipxact:value>0</ipxact:value>
+							</ipxact:reset>
+						</ipxact:resets>
+						<ipxact:bitWidth>1</ipxact:bitWidth>
+					</ipxact:field>
 				</ipxact:register>
 				<ipxact:register>
 					<ipxact:name>STATUS</ipxact:name>

src/CAN_Core/faultConf.vhd

@@ -59,6 +59,9 @@
 --    05.1.2018  Added "erc_capt_r" register for last error capture.
 --    08.5.2018  Added pragmas for one-hot decoding on increment, decrement
 --               error counters.
+--    12.7.2018  Added counters for erasing error counters upon reception of
+--               128 consecutive 11 recessive bits as protocol compliant way
+--               to transfer from Bus-off to Error active!
 --------------------------------------------------------------------------------
 
 Library ieee;
@@ -210,6 +213,25 @@ entity faultConf is
     signal erc_capt_r                :     std_logic_vector(7 downto 0);
 
     signal joined_ctr                :     std_logic_vector(2 downto 0);
+
+    ----------------------------------------------------------------------------
+    -- Counters for Bus-off to Error active transition according to 
+    -- CAN FD standard
+    ----------------------------------------------------------------------------
+
+    -- Counter for 11 consecutive recessive bits!
+    signal cons_rec_ctr              :     natural range 0 to 15;
+
+    -- Counter for 128 ocurrences of 11 consecutive bits
+    signal cons_128_11_rec_ctr       :     natural range 0 to 127;
+
+    -- Command that is generated upon ocurrence of 11 consecutive recessive bits
+    -- 128 times. Upon this command, TX, RX error counters are erased and thus
+    -- Fault confinement state is set to error_active.
+    signal reset_err_counters        :     std_logic;
+
+    -- Counting has started and is in progress...
+    signal cons_128_11_progress      :     std_logic;
  
     ------------------------
     -- Driving bus aliases  
@@ -218,6 +240,7 @@ entity faultConf is
     signal drv_erp                   :     std_logic_vector(7 downto 0);
     signal drv_ctr_val               :     std_logic_vector(8 downto 0);
     signal drv_ctr_sel               :     std_logic_vector(3 downto 0);
+    signal drv_clr_err_ctrs          :     std_logic;
 
     -- Bus off treshold
     constant bus_off_th              :     natural := 255;
@@ -238,6 +261,9 @@ begin
     drv_ctr_sel             <=  drv_bus(DRV_CTR_SEL_HIGH downto
                                       DRV_CTR_SEL_LOW);
 
+    drv_clr_err_ctrs        <=  drv_bus(DRV_ERR_CTR_CLR);
+
+
     -- Counters to output propagation
     tx_counter_out          <=  std_logic_vector(to_unsigned(tx_counter, 9));
     rx_counter_out          <=  std_logic_vector(to_unsigned(rx_counter, 9));
@@ -327,6 +353,10 @@ begin
             if (drv_ctr_sel(0) = '1') then 
                 tx_counter                      <=
                     to_integer(unsigned(drv_ctr_val));
+
+            elsif (reset_err_counters = '1') then
+                tx_counter                      <= 0;
+
             else
                 -- Counting the errors when transmitting
                 if (OP_State = transciever) then
@@ -362,6 +392,10 @@ begin
             if (drv_ctr_sel(1) = '1') then 
                 rx_counter                              <=
                     to_integer(unsigned(drv_ctr_val));
+
+            elsif (reset_err_counters = '1') then
+                rx_counter                      <= 0;
+
             else
 
                 if (OP_State = reciever) then
@@ -605,6 +639,70 @@ begin
           
         end if;
     end process;
+
+
+    ----------------------------------------------------------------------------
+    -- Counting 128 ocurrences of 11 consecutive RECESSIVE bits. Generating
+    -- error counter erase command upon completion!
+    ----------------------------------------------------------------------------
+    err_ctr_erase_proc : process(clk_sys, res_n)
+    begin
+        if (res_n = ACT_RESET) then
+            cons_128_11_progress    <= '0';
+
+            cons_rec_ctr            <= 0;
+            cons_128_11_rec_ctr     <= 0;
+            reset_err_counters      <= '0';
+
+        elsif (rising_edge(clk_sys)) then
+
+            reset_err_counters <= '0';
+
+            -- Setting / Clearing "in progress" flag
+            if (drv_clr_err_ctrs = '1') then
+                cons_128_11_progress <= '1';
+            elsif (reset_err_counters = '1') then
+                cons_128_11_progress <= '0';
+            end if;
+
+            -- Counting 11 consecutive recessive bits!
+            if (cons_128_11_progress = '1') then
+                if (rec_trig = '1') then
+                    if (data_rx = RECESSIVE) then
+                        if (cons_rec_ctr = 10) then
+                            cons_rec_ctr <= 0;
+                        else
+                            cons_rec_ctr <= cons_rec_ctr + 1;
+                        end if;
+                    else
+                        cons_rec_ctr <= 0;
+                    end if;
+                end if;
+            else
+                cons_rec_ctr <= 0;
+            end if;
+
+            -- Counting 128 ocurrences
+            if (cons_128_11_progress = '1') then
+
+                -- 128 ocurrences reached -> Erase error counters command
+                if (cons_128_11_rec_ctr = 127) then
+                    cons_128_11_rec_ctr <= 0;
+                    reset_err_counters <= '1';
+
+                -- Not reached, but 11 consecutive are reached -> add 1!
+                elsif (rec_trig = '1' and data_rx = RECESSIVE and
+                       cons_rec_ctr = 10) then
+                    cons_128_11_rec_ctr <= cons_128_11_rec_ctr + 1;
+                end if;
+            else
+                cons_128_11_rec_ctr <= 0;
+            end if;
+
+        end if;
+    end process;
+
+
   
   -- Internal register to output propagation
   err_capt <= erc_capt_r;

src/CAN_Core/operationControl.vhd

@@ -170,7 +170,11 @@ begin
                     elsif (is_idle = '1') then
                         OP_State_r          <= idle;
                     end if;
-                    
+
+                ----------------------------------------------------------------
+                -- Receiver
+                -- Unit is receiver of a frame.
+                ----------------------------------------------------------------
                 when reciever =>
                     if (is_idle = '1') then
                         OP_State_r          <= idle;

src/Libraries/CAN_FD_register_map.vhd

@@ -247,11 +247,13 @@ package CAN_FD_register_map is
   constant AT_IND                 : natural := 9;
   constant RRB_IND               : natural := 10;
   constant CDO_IND               : natural := 11;
+  constant ERCRST_IND            : natural := 12;
 
   -- COMMAND register reset values
   constant AT_RSTVAL          : std_logic := '0';
   constant RRB_RSTVAL         : std_logic := '0';
   constant CDO_RSTVAL         : std_logic := '0';
+  constant ERCRST_RSTVAL      : std_logic := '0';
 
   ------------------------------------------------------------------------------
   -- STATUS register

src/Libraries/CANconstants.vhd

@@ -454,6 +454,8 @@ package CANconstants is
     constant DRV_CTR_SEL_LOW  : natural := 425;
     constant DRV_CTR_SEL_HIGH : natural := 428;
 
+    constant DRV_ERR_CTR_CLR  : natural := 429;
+
     -- Operation control FSM
     constant DRV_CAN_FD_ENA_INDEX    : natural := 460;
     constant DRV_RTR_PREF_INDEX      : natural := 461;

src/Registers_Memory_Interface/canfd_registers.vhd

@@ -250,6 +250,7 @@ entity canfd_registers is
     signal release_recieve        :     std_logic;
     signal abort_transmittion     :     std_logic;
     signal ack_forb               :     std_logic;
+    signal clr_err_ctrs           :     std_logic;
 
     -- Retransmit limited is enabled
     signal retr_lim_ena           :     std_logic;
@@ -442,7 +443,8 @@ architecture rtl of canfd_registers is
         signal CAN_enable             :out  std_logic;
         signal FD_type                :out  std_logic;
         signal mode_reg               :out  std_logic_vector(5 downto 0);
-        signal rtsopt                 :out  std_logic
+        signal rtsopt                 :out  std_logic;
+        signal clr_err_ctrs           :out  std_logic
     ) is
     begin
     
@@ -544,6 +546,8 @@ architecture rtl of canfd_registers is
         int_mask_clear              <= INT_MASK_CLR_RSTVAL;
 
         rtsopt                      <= RTSOP_RSTVAL;
+
+        clr_err_ctrs                <= ERCRST_RSTVAL;
     end procedure;
   
   
@@ -734,7 +738,8 @@ begin
             intLoopbackEna     ,log_trig_config        ,
             log_capt_config    ,log_cmd                ,rx_ctr_set          ,
             tx_ctr_set         ,ctr_val_set            ,CAN_enable          ,
-            FD_type            ,mode_reg               ,rtsopt
+            FD_type            ,mode_reg               ,rtsopt              ,
+            clr_err_ctrs
             );
 
             RX_buff_read_first    <= false;
@@ -776,7 +781,7 @@ begin
                 log_capt_config    ,log_cmd                ,
                 rx_ctr_set         ,tx_ctr_set             ,
                 ctr_val_set        ,CAN_enable             ,FD_type            ,
-                mode_reg           ,rtsopt
+                mode_reg           ,rtsopt                 ,clr_err_ctrs
                 );
 
                 RX_buff_read_first    <= false;
@@ -842,6 +847,7 @@ begin
                 ctr_val_set               <=  (OTHERS =>'0');
                 rx_ctr_set                <=  '0';
                 tx_ctr_set                <=  '0';
+                clr_err_ctrs              <=  '0';
                 ack_forb                  <=  ack_forb;
                 data_out_int              <=  (OTHERS=>'0');
                 log_cmd                   <=  (OTHERS =>'0');
@@ -908,6 +914,7 @@ begin
                             write_be_s(clear_overrun, CDO_IND, data_in, sbe);
                             write_be_s(release_recieve, RRB_IND, data_in, sbe);
                             write_be_s(abort_transmittion, AT_IND, data_in, sbe);
+                            write_be_s(clr_err_ctrs, ERCRST_IND, data_in, sbe);
 
                             --Status register is read only!
 
@@ -1846,7 +1853,7 @@ begin
     drv_bus(609 downto 601)                           <=  (OTHERS => '0');
     drv_bus(579 downto 570)                           <=  (OTHERS => '0');
     drv_bus(519 downto 511)                           <=  (OTHERS => '0');
-    drv_bus(444 downto 429)                           <=  (OTHERS => '0');
+    drv_bus(444 downto 430)                           <=  (OTHERS => '0');
 
     drv_bus(1023 downto 876)                          <=  (OTHERS => '0');
 
@@ -1938,6 +1945,8 @@ begin
     drv_bus(DRV_CTR_VAL_HIGH downto DRV_CTR_VAL_LOW)  <=  erctr_pres_value;
     drv_bus(DRV_CTR_SEL_HIGH downto DRV_CTR_SEL_LOW)  <=  erctr_pres_mask;
 
+    drv_bus(DRV_ERR_CTR_CLR)                          <=  clr_err_ctrs;
+
     -- CAN Core
     drv_bus(DRV_ABORT_TRAN_INDEX)                     <=  abort_transmittion;