From ac238324027c69ffb389f306825989537bbaecaa Mon Sep 17 00:00:00 2001 From: "Ille, Ondrej, Ing" Date: Fri, 16 Nov 2018 18:12:02 +0100 Subject: [PATCH] Added generic polarity to reset synchroniser --- src/CAN_top_level.vhd | 7 ++- src/Libraries/CANcomponents.vhd | 14 ++--- src/rst_sync.vhd | 33 +++++++----- src/sig_sync.vhd | 92 +++++++++++++++++++++++++++++++++ 4 files changed, 126 insertions(+), 20 deletions(-) create mode 100644 src/sig_sync.vhd diff --git a/src/CAN_top_level.vhd b/src/CAN_top_level.vhd index 115224b9..6c709860 100644 --- a/src/CAN_top_level.vhd +++ b/src/CAN_top_level.vhd @@ -492,10 +492,13 @@ begin -- synthesis translate_on rst_sync_comp : rst_sync + generic map( + reset_polarity => ACT_RESET + ) port map( clk => clk_sys, - arst_n => res_n, - rst_n => res_n_sync + arst => res_n, + rst => res_n_sync ); reg_comp : canfd_registers diff --git a/src/Libraries/CANcomponents.vhd b/src/Libraries/CANcomponents.vhd index 96434136..d0c2ccde 100644 --- a/src/Libraries/CANcomponents.vhd +++ b/src/Libraries/CANcomponents.vhd @@ -859,12 +859,14 @@ package CANcomponents is -- Asynchronous resset synchroniser ---------------------------------------------------------------------------- component rst_sync is - port ( - signal clk : in std_logic; - signal arst_n : in std_logic; - signal rst_n : out std_logic - ); - end component; + generic ( + constant reset_polarity : std_logic + ); + port ( + signal clk : in std_logic; + signal arst : in std_logic; + signal rst : out std_logic + ); ---------------------------------------------------------------------------- -- APB Interface diff --git a/src/rst_sync.vhd b/src/rst_sync.vhd index 84a6c78d..6589efe6 100644 --- a/src/rst_sync.vhd +++ b/src/rst_sync.vhd @@ -41,35 +41,44 @@ -------------------------------------------------------------------------------- -- Purpose: --- Asynchronouse reset synchroniser to avoid problems with Reset recovery time. +-- Asynchronous reset synchroniser. -------------------------------------------------------------------------------- -- Revision History: -- 27.11.2017 Created file --- +-- 16.11.2018 Added generic reset polarity -------------------------------------------------------------------------------- Library ieee; use ieee.std_logic_1164.all; entity rst_sync is + generic ( + constant reset_polarity : std_logic + ); port ( - signal clk : in std_logic; - signal arst_n : in std_logic; - signal rst_n : out std_logic + signal clk : in std_logic; + signal arst : in std_logic; + signal rst : out std_logic ); end rst_sync; architecture rtl of rst_sync is - signal rff : std_logic; + + -- Synchroniser registers + signal rff : std_logic; + begin - process (clk, arst_n) + + -- Reset synchroniser process + rst_sync_proc : process (clk, arst_n) begin - if (arst_n = '0') then - rff <= '0'; - rst_n <= '0'; + if (arst = reset_polarity) then + rff <= reset_polarity; + rst <= reset_polarity; elsif (rising_edge(clk)) then - rff <= '1'; - rst_n <= rff; + rff <= not (reset_polarity); + rst <= rff; end if; end process; + end rtl; diff --git a/src/sig_sync.vhd b/src/sig_sync.vhd new file mode 100644 index 00000000..c6d7deb1 --- /dev/null +++ b/src/sig_sync.vhd @@ -0,0 +1,92 @@ +-------------------------------------------------------------------------------- +-- +-- CTU CAN FD IP Core +-- Copyright (C) 2015-2018 +-- +-- Authors: +-- Ondrej Ille +-- Martin Jerabek +-- +-- Project advisors: +-- Jiri Novak +-- Pavel Pisa +-- +-- Department of Measurement (http://meas.fel.cvut.cz/) +-- Faculty of Electrical Engineering (http://www.fel.cvut.cz) +-- Czech Technical University (http://www.cvut.cz/) +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this VHDL component and associated documentation files (the "Component"), +-- to deal in the Component without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Component, and to permit persons to whom the +-- Component is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Component. +-- +-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS +-- IN THE COMPONENT. +-- +-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. +-- Anybody who wants to implement this IP core on silicon has to obtain a CAN +-- protocol license from Bosch. +-- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Purpose: +-- Two Flip-flop asynchronous signal synchroniser. Synthesizes as two DFFs. +-- Simulation behaviour is like so: +-- 1. If t_setup and t_hold are not corrupted, two clock cycle delay is +-- introduced. +-- 2. If t_setup or t_hold are corrupted, +-------------------------------------------------------------------------------- +-- Revision History: +-- 16.11.2018 Created file +-------------------------------------------------------------------------------- + +Library ieee; +use ieee.std_logic_1164.all; + +entity sig_sync is + generic ( + constant t_setup : time := 0 ps; + constant t_hold : time := 0 ps; + constant timing_check : boolean := true; + ); + port ( + signal clk : in std_logic; + signal async : in std_logic; + signal sync : out std_logic + ); +end rst_sync; + +architecture rtl of rst_sync is + + -- Synchroniser registers + signal rff : std_logic; + +begin + + -- Signal synchroniser process. + rst_sync_proc : process (clk) + begin + if (rising_edge(clk)) then + rff <= async; + sync <= rff; + end if; + end process; + + -- Check for timing violations on second DFF + timing_check_proc : proces + begin + + end process; + +end rtl; -- GitLab