Commit ab817535 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '330-split-register-list-from-rtl' into 'master'

Resolve "Split register list from RTL"

Closes #330

See merge request !330
parents 4d0f9fa8 21e06043
Pipeline #15897 passed with stage
in 17 seconds
......@@ -3949,6 +3949,49 @@ CTU CAN FD contains Error code capture register.
Error code capture is updated in sample point of a bit where error was
detected.
Error code capture is readable via ERR_CAPT register.
CAN FD standard does not defined types of errors as mutually exclusive
(e.g.
bit error and stuff error may occur at the same time when transmitted stuff
bit value is corrupted to opposite value).
In such case, Error code capture captures only one type of error with highest
priority.
Priorities of error types are defined as (Form error having the highest
priority):
\end_layout
\begin_layout Enumerate
Form error
\end_layout
\begin_layout Enumerate
Bit error
\end_layout
\begin_layout Enumerate
CRC error
\end_layout
\begin_layout Enumerate
ACK error
\end_layout
\begin_layout Enumerate
Stuff error
\end_layout
\begin_layout Description
Note Stuff error which occured during fixed bit stuffing method of CAN FD
frame is reported as Form error in Error code capture.
\end_layout
\begin_layout Description
Note
\begin_inset space ~
\end_inset
2 There is an exception to above mentioned error priority order.
If dominant stuff bit is sent during arbitration field and recessive value
is sampled, then this is captured as Stuff error, not as Bit error.
\end_layout
\begin_layout Subsection
......
Subproject commit 4caf19087cc058d1b55bd7f8b107d5e73d167eba
Subproject commit 58c058cc9103b259a10a50406454fe978171f646
......@@ -4,4 +4,9 @@ d="$(dirname "$0")"
# Note: the script uses relative paths and must be called from this directory
cd "$d"
python3 update_reg_map.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --updVHDLPackage True --updHeaderFile True --updLyxDocs True --updRTLRegMap True
python3 update_reg_map.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml \
--updVHDLPackage True \
--updHeaderFile True \
--updLyxDocs True \
--updRTLRegMap True \
--updTbPackage True
......@@ -38,6 +38,7 @@ from pyXact_generator.gen_lib import *
from pyXact_generator.HeaderAddrGeneratorWrapper import HeaderAddrGeneratorWrapper
from pyXact_generator.LyxAddrGeneratorWrapper import LyxAddrGeneratorWrapper
from pyXact_generator.VhdlAddrGeneratorWrapper import VhdlAddrGeneratorWrapper
from pyXact_generator.VhdlTbAddrGeneratorWrapper import VhdlTbAddrGeneratorWrapper
from pyXact_generator.VhdlRegMapGeneratorWrapper import VhdlRegMapGeneratorWrapper
MIT_LICENSE_PATH = "../LICENSE"
......@@ -67,6 +68,11 @@ def parse_args():
parser.add_argument('--updRTLRegMap', dest='updRTLRegMap', help="""Whether VHDL
RTL register map should be generated.
(../src/Registers_Memory_Interface/generated)""")
parser.add_argument('--updTbPackage', dest='updTbPackage', help="""Whether Testbench
package with register list should be generated
(../test/lib)""")
return parser.parse_args();
......@@ -138,6 +144,23 @@ def ctu_can_update_vhdl_rtl(specPath, licensePath, memMap, wordWidthBit, outDir)
vhdlRTLGeneratorWrapper.do_update()
def ctu_can_update_vhdl_tb_package(specPath, licensePath, memMap,
wordWidthBit, outPath, packName):
"""
Update VHDL Testbench packages of CTU CAN FD register maps.
"""
tbAddrGeneratorWrapper = VhdlTbAddrGeneratorWrapper()
tbAddrGeneratorWrapper.xactSpec = specPath
tbAddrGeneratorWrapper.licPath = licensePath
tbAddrGeneratorWrapper.memMap = memMap
tbAddrGeneratorWrapper.wordWidth = wordWidthBit
tbAddrGeneratorWrapper.outFile = outPath
tbAddrGeneratorWrapper.packName = packName
tbAddrGeneratorWrapper.do_update()
if __name__ == '__main__':
args = parse_args()
print( 80 * "*")
......@@ -227,7 +250,7 @@ if __name__ == '__main__':
###########################################################################
# Generate VHDL RTL codes
###########################################################################
###########################################################################
if (str_arg_to_bool(args.updRTLRegMap)):
print("Generating CAN FD memory registers Documentation...\n")
......@@ -242,7 +265,24 @@ if __name__ == '__main__':
# visualisaion only
print("\nDone\n")
###########################################################################
# Generate Testbench package
###########################################################################
if (str_arg_to_bool(args.updTbPackage)):
print("Generating Testbench package...\n")
ctu_can_update_vhdl_tb_package(specPath=args.xactSpec,
licensePath=MIT_LICENSE_PATH,
memMap="CAN_Registers",
wordWidthBit=32,
outPath="../test/lib/can_fd_tb_register_map.vhd",
packName="can_fd_tb_register_map")
print("\nDone\n")
print( 80 * "*")
print("** Finished")
print(80 * "*")
......
......@@ -135,6 +135,7 @@ architecture rtl of bit_stuffing is
signal same_bits_q : unsigned(2 downto 0);
signal same_bits_add : unsigned(2 downto 0);
signal same_bits_d : unsigned(2 downto 0);
signal tx_no_sof_val : unsigned(2 downto 0);
-- Halt for CAN Core
signal data_halt_q : std_logic;
......@@ -327,17 +328,25 @@ begin
---------------------------------------------------------------------------
same_bits_add <= (same_bits_q + 1) mod 8;
---------------------------------------------------------------------------
-- Preset value in case of start of transmission without transmission of
-- SOF (as result of Sampling dominant and considering this as SOF!):
-- 1. If we transmitt dominant, we put two, this accounts for SOF + first
-- transmitted bit of ID.
-- 2. If we transmitt recessive, we put one, this accounts only for first
-- transmitted bit of ID.
---------------------------------------------------------------------------
tx_no_sof_val <= "010" when (data_in = DOMINANT) else
"001";
---------------------------------------------------------------------------
-- Next value for counter of equal consecutive bits:
-- 1. Set to 2 when transmission started without SOF and first bit of
-- Base ID is dominant! This accounts for SOF + Base ID (1)!
-- 1. Preset to special value when we don't transmit SOF!
-- 2. Reset
-- 3. Increment if not reset when processing bit.
-- 4. Keep original value otherwise.
---------------------------------------------------------------------------
same_bits_d <= "010" when (tx_frame_no_sof = '1' and
data_in = DOMINANT) else
same_bits_d <= tx_no_sof_val when (tx_frame_no_sof = '1') else
"001" when (same_bits_rst = '1') else
same_bits_add when (bst_trigger = '1') else
same_bits_q;
......
......@@ -49,26 +49,6 @@ use ieee.std_logic_1164.all;
package can_fd_frame_format is
------------------------------------------------------------------------------
-- Common types
------------------------------------------------------------------------------
type t_reg_type is (
reg_none,
reg_write_only,
reg_read_only,
reg_read_write,
reg_read_write_once
);
type t_memory_reg is record
address : std_logic_vector(11 downto 0);
size : integer;
reg_type : t_reg_type;
reset_val : std_logic_vector(31 downto 0);
is_implem : std_logic_vector(31 downto 0);
end record;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Address block: CAN_FD_Frame_format
......@@ -84,51 +64,6 @@ package can_fd_frame_format is
constant DATA_5_8_W_ADR : std_logic_vector(11 downto 0) := x"014";
constant DATA_61_64_W_ADR : std_logic_vector(11 downto 0) := x"04C";
------------------------------------------------------------------------------
-- Register list
------------------------------------------------------------------------------
type t_CAN_FD_Frame_format_list is array (0 to 6) of t_memory_reg;
constant CAN_FD_Frame_format_list : t_CAN_FD_Frame_format_list :=(
(address => FRAME_FORM_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000001111111011101111"),
(address => IDENTIFIER_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => TIMESTAMP_L_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => TIMESTAMP_U_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => DATA_1_4_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => DATA_5_8_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => DATA_61_64_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111")
);
------------------------------------------------------------------------------
-- FRAME_FORM_W register
--
......
This diff is collapsed.
......@@ -55,7 +55,7 @@
-- @2. Wait until sample point in Node 1 and measure number of clock cycles
-- till next sample point. Check that it corresponds to pre-computed value!
-- @3. Send frame by Node 1 and wait until it is sent. Read frame from Node 2
-- and check they are matching. Do vice-versa from Node 2 to Node 1!
-- and check they are matching.
--
-- @TestInfoEnd
--------------------------------------------------------------------------------
......@@ -118,7 +118,7 @@ package body btr_feature is
rand_int_v(rand_ctr, 63, bus_timing.ph2_nbt);
-- Longer TQ is possible but test run-time is killing us!
rand_int_v(rand_ctr, 63, bus_timing.tq_nbt);
rand_int_v(rand_ctr, 32, bus_timing.tq_nbt);
rand_int_v(rand_ctr, 33, bus_timing.sjw_nbt);
-- Configure delay of TX -> RX so that for any generated bit-rate, it
......@@ -228,11 +228,21 @@ package body btr_feature is
-----------------------------------------------------------------------
-- @3. Send frame by Node 1 and wait until it is sent. Read frame from
-- Node 2 and check they are matching. Do vice-versa from Node 2 to
-- Node 1!
-- Node 2 and check they are matching.
-----------------------------------------------------------------------
info("Step 3");
-- Shorten length of generated frame to max 4 data bytes! The thing is
-- that if generated bit rate is too low, and data field length too
-- high, test run time explodes! It has no sense to test long data fields
-- on any bit-rate since its functionality should not depend on it!
CAN_generate_frame(rand_ctr, CAN_frame_1);
if (CAN_frame_1.data_length > 4) then
CAN_frame_1.data_length := 4;
decode_length(CAN_frame_1.data_length, CAN_frame_1.dlc);
end if;
CAN_send_frame(CAN_frame_1, 1, ID_1, mem_bus(1), frame_sent);
CAN_wait_frame_sent(ID_2, mem_bus(2));
CAN_read_frame(CAN_frame_2, ID_2, mem_bus(2));
......
......@@ -159,7 +159,11 @@ package body err_capt_arb_bit_feature is
check (stat_1.error_transmission, "Error frame is being transmitted!");
CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
check(err_capt.err_type = can_err_bit, "Bit error detected!");
-- If Dominant stuff bit is sent and recessive is monitored, then this
-- can be detected as Stuff Error, not as bit Error!
check(err_capt.err_type = can_err_bit or err_capt.err_type = can_err_stuff,
"Bit or Stuff error detected!");
check(err_capt.err_pos = err_pos_arbitration, "Error detected in Arbitration!");
CAN_wait_bus_idle(ID_1, mem_bus(1));
......
......@@ -146,7 +146,7 @@ package body err_capt_crc_bit_feature is
crc_len := 15; -- CRC 15 (CAN 2.0 frames have no Stuff count)!
end if;
-- Wait for Random amount of time!
-- Wait for Random amount of bits, but not longer than CRC field!
rand_int_v(rand_ctr, crc_len - 1, tmp);
info("Waiting for: " & integer'image(tmp) & " bits!");
for i in 1 to tmp loop
......@@ -165,7 +165,22 @@ package body err_capt_crc_bit_feature is
check (stat_1.error_transmission, "Error frame is being transmitted!");
CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
check(err_capt.err_type = can_err_bit, "Bit error detected!");
-----------------------------------------------------------------------
-- It might happend that we corrupt a bit which is just stuff bit (due
-- to randomization). If this is a CAN FD frame, this will be considered
-- as form error (stuff error during fixed bit stuffing shall be reported
-- as form error). In such case, form error has higher priority than
-- stuff error, so form error is reported. Tolerate this as this is not
-- a bug!
-----------------------------------------------------------------------
if (frame_1.frame_format = FD_CAN) then
check(err_capt.err_type = can_err_bit or
err_capt.err_type = can_err_form, "Bit or Form error detected!");
else
check(err_capt.err_type = can_err_bit, "Bit error detected!");
end if;
check(err_capt.err_pos = err_pos_crc, "Error detected in CRC field!");
CAN_wait_bus_idle(ID_1, mem_bus(1));
......
......@@ -141,7 +141,18 @@ package body err_capt_ctrl_bit_feature is
for i in 1 to 4 loop
info ("Inner Loop: " & integer'image(i));
CAN_generate_frame(rand_ctr, frame_1);
-- Detect patterns in which stuff bit might be placed. In such
-- case, avoid it. Because if we stuff the same value of bit as
-- we are trying to force, error frame will not be sent (obviously,
-- bus has equal value as is sent) and test will fail!
if (frame_1.dlc(3) = frame_1.dlc(2)) then
-- It is enough to break first two equal bits!
frame_1.dlc(3) := not frame_1.dlc(2);
decode_dlc(frame_1.dlc, frame_1.data_length);
end if;
-- ID is not important in this TC. Avoid overflows of high generated
-- IDs on Base IDs!
frame_1.identifier := 10;
......
......@@ -126,7 +126,7 @@ package body error_rules_a_feature is
wait until iout(2).can_tx = DOMINANT;
force_bus_level(RECESSIVE, so.bl_force, so.bl_inject);
CAN_wait_sample_point(iout(2).stat_bus);
CAN_wait_sample_point(iout(2).stat_bus, false);
wait for 20 ns;
get_controller_status(status, ID_2, mem_bus(2));
......@@ -167,7 +167,7 @@ package body error_rules_a_feature is
wait until iout(2).can_tx = DOMINANT;
force_bus_level(RECESSIVE, so.bl_force, so.bl_inject);
CAN_wait_sample_point(iout(2).stat_bus);
CAN_wait_sample_point(iout(2).stat_bus, false);
wait for 35 ns; -- To account for all pipeline stages delay!
get_controller_status(status, ID_2, mem_bus(2));
......@@ -180,10 +180,10 @@ package body error_rules_a_feature is
get_controller_status(status, ID_1, mem_bus(1));
end loop;
-- Now force the bus low for 10 bit times
-- Now force the bus low for 16 bit times
force_bus_level(RECESSIVE, so.bl_force, so.bl_inject);
for i in 0 to 15 loop
CAN_wait_sample_point(iout(1).stat_bus);
CAN_wait_sample_point(iout(1).stat_bus, false);
end loop;
wait for 20 ns;
release_bus_level(so.bl_force);
......
......@@ -81,6 +81,8 @@ use lib.cmn_lib.all;
use lib.drv_stat_pkg.all;
use lib.reduce_lib.all;
use lib.can_config.all;
use lib.tb_reg_map_defs_pkg.All;
use lib.can_fd_tb_register_map.All;
use lib.CAN_FD_register_map.all;
......
......@@ -89,6 +89,7 @@
context work.ctu_can_synth_context;
context work.ctu_can_test_context;
--Library ieee;
use lib.pkg_feature_exec_dispath.all;
package ssp_cfg_feature is
......@@ -99,10 +100,47 @@ package ssp_cfg_feature is
signal mem_bus : inout mem_bus_arr_t;
signal bus_level : in std_logic
);
procedure correct_ssp_offset(
ssp_offset_generated : in std_logic_vector(7 downto 0);
bus_timing : in bit_time_config_type;
ssp_offset_corrected : out std_logic_vector(7 downto 0)
);
end package;
package body ssp_cfg_feature is
---------------------------------------------------------------------------
-- Data bit time is generated random. Also SSP_OFFSET is generated random.
-- We set real delay from CAN_TX to CAN_RX in TB also to random generated
-- value. If generated SSP_OFFSET is higher than duration of bit, then
-- we will never sample correct value, because we just sample next bit
-- already! So we need to constrain configured SSP_OFFSET to less than
-- data bit time!
---------------------------------------------------------------------------
procedure correct_ssp_offset(
ssp_offset_generated : in std_logic_vector(7 downto 0);
bus_timing : in bit_time_config_type;
ssp_offset_corrected : out std_logic_vector(7 downto 0)
) is
variable bit_time_length : natural;
begin
bit_time_length := bus_timing.tq_dbt * (1 + bus_timing.prop_dbt +
bus_timing.ph1_dbt + bus_timing.ph2_dbt);
if (to_integer(unsigned(ssp_offset_generated)) >= bit_time_length) then
ssp_offset_corrected := std_logic_vector(to_unsigned(bit_time_length - 1, 8));
info("Correcting SSP offset. Bit time length: " &
integer'image(bit_time_length) & " cycles. New SSP offset value:" &
integer'image(to_integer(unsigned(ssp_offset_corrected))));
else
ssp_offset_corrected := ssp_offset_generated;
end if;
end procedure;
procedure ssp_cfg_feature_exec(
signal so : out feature_signal_outputs_t;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
......@@ -132,7 +170,8 @@ package body ssp_cfg_feature is
variable num_bit_waits : natural;
variable num_bit_waits_max : natural;
variable tx_val : std_logic;
variable bit_rate : real;
variable cycles_per_bit : integer;
begin
-----------------------------------------------------------------------
......@@ -151,12 +190,44 @@ package body ssp_cfg_feature is
bus_timing.tq_nbt := 4;
bus_timing.sjw_nbt := 5;
-- Should be 2 Mbit/s
bus_timing.prop_dbt := 10;
bus_timing.ph1_dbt := 20;
bus_timing.ph2_dbt := 19;
bus_timing.tq_dbt := 1;
bus_timing.sjw_dbt := 5;
-- Generate random data bit timing!
rand_int_v(rand_ctr, 63, bus_timing.prop_dbt);
rand_int_v(rand_ctr, 31, bus_timing.ph1_dbt);
rand_int_v(rand_ctr, 31, bus_timing.ph2_dbt);
-- Constrain time quanta to something realistinc for data phase so
-- that we don't have too long run times!
rand_int_v(rand_ctr, 4, bus_timing.tq_dbt);
rand_int_v(rand_ctr, 33, bus_timing.sjw_dbt);
-- Minimal time quanta
if (bus_timing.tq_dbt = 0) then
bus_timing.tq_dbt := 1;
end if;
cycles_per_bit := bus_timing.tq_dbt * (1 + bus_timing.prop_dbt +
bus_timing.ph1_dbt + bus_timing.ph2_dbt);
-- Constrain minimal bit times
if (cycles_per_bit < 7) then
bus_timing.prop_dbt := 7;
end if;
if (bus_timing.tq_dbt = 1 and bus_timing.ph2_dbt = 1) then
bus_timing.ph2_dbt := 2;
end if;
cycles_per_bit := bus_timing.tq_dbt * (1 + bus_timing.prop_dbt +
bus_timing.ph1_dbt + bus_timing.ph2_dbt);
info("Cycles per bit:" & integer'image(cycles_per_bit));
info ("Generated data bit time bit-rate:");
info ("TQ: " & integer'image(bus_timing.tq_dbt));
info ("PROP: " & integer'image(bus_timing.prop_dbt));
info ("PH1: " & integer'image(bus_timing.ph1_dbt));
info ("PH2: " & integer'image(bus_timing.ph2_dbt));
bit_rate := 100000000.0 / (real(cycles_per_bit));
info ("Data bit rate: " & real'image(bit_rate/1000000.0) & " Mbit/s");
-- We configure Nominal bit-rate to 500 Kbit/s so that generated
-- TRV_DELAY will not cause error frames in arbitration bit-rate!
......@@ -202,9 +273,12 @@ package body ssp_cfg_feature is
info("TRV_DELAY + Offset");
ssp_source := ssp_meas_n_offset;
rand_logic_vect_v (rand_ctr, ssp_offset_var, 0.3);
info("Generated SSP offset: " & integer'image(to_integer(unsigned(ssp_offset_var))));
correct_ssp_offset(ssp_offset_var, bus_timing, ssp_offset_var);
-- SSP position is offset + delay
info("SSP offset: " & integer'image(to_integer(unsigned(ssp_offset_var))));
info("Post correction SSP offset: " & integer'image(to_integer(unsigned(ssp_offset_var))));
info("Trv delay div: " & integer'image(rand_trv_delay / 10));
ssp_pos := to_integer(unsigned(ssp_offset_var)) + rand_trv_delay / 10;
......@@ -238,6 +312,10 @@ package body ssp_cfg_feature is
ssp_source := ssp_offset;
rand_logic_vect_v (rand_ctr, ssp_offset_var, 0.3);
correct_ssp_offset(ssp_offset_var, bus_timing, ssp_offset_var);
info("Post correction SSP offset: " & integer'image(to_integer(unsigned(ssp_offset_var))));
-- Here lengthen the SSP offset so that we are sufficiently over TRV_DELAY!
-- It should be enough to lengthen it by two clock cycles (input delay of
-- CTU CAN FD) + one cycle reserve for truncation of non-multiple of 10
......@@ -282,6 +360,7 @@ package body ssp_cfg_feature is
CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent);
CAN_wait_pc_state(pc_deb_control, ID_1, mem_bus(1));
CAN_wait_not_pc_state(pc_deb_control, ID_1, mem_bus(1));
-- +10 is to cover some part of CRC
......
......@@ -112,6 +112,7 @@ package body tx_from_intermission_feature is
-- transmission will be started. Insert CAN frame to Node 1 during
-- transmission of frame from Node 2 and wait until Intermission.
-----------------------------------------------------------------------
info("Step 1");
CAN_generate_frame(rand_ctr, frame_1);
CAN_send_frame(frame_1, 1, ID_2, mem_bus(2), frame_sent);
......@@ -133,6 +134,7 @@ package body tx_from_intermission_feature is
-- until frame is sent, and check it is properly receieved by Node 2
-- (Node 2 should have turned receiver).
-----------------------------------------------------------------------
info("Step 2");
CAN_wait_sample_point(iout(1).stat_bus, false);
CAN_wait_sample_point(iout(1).stat_bus, false);
......
......@@ -87,6 +87,7 @@ USE work.randomLib.All;
use work.can_constants.all;
use work.drv_stat_pkg.all;
use work.can_config.all;
use work.tb_reg_map_defs_pkg.All;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
......
This diff is collapsed.
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Package with types used by register map generator generated packages for TB.
--
--------------------------------------------------------------------------------
-- Revision History:
-- 17.01.2020 Created file