Commit ab817535 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '330-split-register-list-from-rtl' into 'master'

Resolve "Split register list from RTL"

Closes #330

See merge request !330
parents 4d0f9fa8 21e06043
Pipeline #15897 passed with stage
in 17 seconds
......@@ -3949,6 +3949,49 @@ CTU CAN FD contains Error code capture register.
Error code capture is updated in sample point of a bit where error was
detected.
Error code capture is readable via ERR_CAPT register.
CAN FD standard does not defined types of errors as mutually exclusive
(e.g.
bit error and stuff error may occur at the same time when transmitted stuff
bit value is corrupted to opposite value).
In such case, Error code capture captures only one type of error with highest
priority.
Priorities of error types are defined as (Form error having the highest
priority):
\end_layout
\begin_layout Enumerate
Form error
\end_layout
\begin_layout Enumerate
Bit error
\end_layout
\begin_layout Enumerate
CRC error
\end_layout
\begin_layout Enumerate
ACK error
\end_layout
\begin_layout Enumerate
Stuff error
\end_layout
\begin_layout Description
Note Stuff error which occured during fixed bit stuffing method of CAN FD
frame is reported as Form error in Error code capture.
\end_layout
\begin_layout Description
Note
\begin_inset space ~
\end_inset
2 There is an exception to above mentioned error priority order.
If dominant stuff bit is sent during arbitration field and recessive value
is sampled, then this is captured as Stuff error, not as Bit error.
\end_layout
\begin_layout Subsection
......
Subproject commit 4caf19087cc058d1b55bd7f8b107d5e73d167eba
Subproject commit 58c058cc9103b259a10a50406454fe978171f646
......@@ -4,4 +4,9 @@ d="$(dirname "$0")"
# Note: the script uses relative paths and must be called from this directory
cd "$d"
python3 update_reg_map.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --updVHDLPackage True --updHeaderFile True --updLyxDocs True --updRTLRegMap True
python3 update_reg_map.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml \
--updVHDLPackage True \
--updHeaderFile True \
--updLyxDocs True \
--updRTLRegMap True \
--updTbPackage True
......@@ -38,6 +38,7 @@ from pyXact_generator.gen_lib import *
from pyXact_generator.HeaderAddrGeneratorWrapper import HeaderAddrGeneratorWrapper
from pyXact_generator.LyxAddrGeneratorWrapper import LyxAddrGeneratorWrapper
from pyXact_generator.VhdlAddrGeneratorWrapper import VhdlAddrGeneratorWrapper
from pyXact_generator.VhdlTbAddrGeneratorWrapper import VhdlTbAddrGeneratorWrapper
from pyXact_generator.VhdlRegMapGeneratorWrapper import VhdlRegMapGeneratorWrapper
MIT_LICENSE_PATH = "../LICENSE"
......@@ -67,6 +68,11 @@ def parse_args():
parser.add_argument('--updRTLRegMap', dest='updRTLRegMap', help="""Whether VHDL
RTL register map should be generated.
(../src/Registers_Memory_Interface/generated)""")
parser.add_argument('--updTbPackage', dest='updTbPackage', help="""Whether Testbench
package with register list should be generated
(../test/lib)""")
return parser.parse_args();
......@@ -138,6 +144,23 @@ def ctu_can_update_vhdl_rtl(specPath, licensePath, memMap, wordWidthBit, outDir)
vhdlRTLGeneratorWrapper.do_update()
def ctu_can_update_vhdl_tb_package(specPath, licensePath, memMap,
wordWidthBit, outPath, packName):
"""
Update VHDL Testbench packages of CTU CAN FD register maps.
"""
tbAddrGeneratorWrapper = VhdlTbAddrGeneratorWrapper()
tbAddrGeneratorWrapper.xactSpec = specPath
tbAddrGeneratorWrapper.licPath = licensePath
tbAddrGeneratorWrapper.memMap = memMap
tbAddrGeneratorWrapper.wordWidth = wordWidthBit
tbAddrGeneratorWrapper.outFile = outPath
tbAddrGeneratorWrapper.packName = packName
tbAddrGeneratorWrapper.do_update()
if __name__ == '__main__':
args = parse_args()
print( 80 * "*")
......@@ -227,7 +250,7 @@ if __name__ == '__main__':
###########################################################################
# Generate VHDL RTL codes
###########################################################################
###########################################################################
if (str_arg_to_bool(args.updRTLRegMap)):
print("Generating CAN FD memory registers Documentation...\n")
......@@ -242,7 +265,24 @@ if __name__ == '__main__':
# visualisaion only
print("\nDone\n")
###########################################################################
# Generate Testbench package
###########################################################################
if (str_arg_to_bool(args.updTbPackage)):
print("Generating Testbench package...\n")
ctu_can_update_vhdl_tb_package(specPath=args.xactSpec,
licensePath=MIT_LICENSE_PATH,
memMap="CAN_Registers",
wordWidthBit=32,
outPath="../test/lib/can_fd_tb_register_map.vhd",
packName="can_fd_tb_register_map")
print("\nDone\n")
print( 80 * "*")
print("** Finished")
print(80 * "*")
......
......@@ -135,6 +135,7 @@ architecture rtl of bit_stuffing is
signal same_bits_q : unsigned(2 downto 0);
signal same_bits_add : unsigned(2 downto 0);
signal same_bits_d : unsigned(2 downto 0);
signal tx_no_sof_val : unsigned(2 downto 0);
-- Halt for CAN Core
signal data_halt_q : std_logic;
......@@ -327,17 +328,25 @@ begin
---------------------------------------------------------------------------
same_bits_add <= (same_bits_q + 1) mod 8;
---------------------------------------------------------------------------
-- Preset value in case of start of transmission without transmission of
-- SOF (as result of Sampling dominant and considering this as SOF!):
-- 1. If we transmitt dominant, we put two, this accounts for SOF + first
-- transmitted bit of ID.
-- 2. If we transmitt recessive, we put one, this accounts only for first
-- transmitted bit of ID.
---------------------------------------------------------------------------
tx_no_sof_val <= "010" when (data_in = DOMINANT) else
"001";
---------------------------------------------------------------------------
-- Next value for counter of equal consecutive bits:
-- 1. Set to 2 when transmission started without SOF and first bit of
-- Base ID is dominant! This accounts for SOF + Base ID (1)!
-- 1. Preset to special value when we don't transmit SOF!
-- 2. Reset
-- 3. Increment if not reset when processing bit.
-- 4. Keep original value otherwise.
---------------------------------------------------------------------------
same_bits_d <= "010" when (tx_frame_no_sof = '1' and
data_in = DOMINANT) else
same_bits_d <= tx_no_sof_val when (tx_frame_no_sof = '1') else
"001" when (same_bits_rst = '1') else
same_bits_add when (bst_trigger = '1') else
same_bits_q;
......
......@@ -49,26 +49,6 @@ use ieee.std_logic_1164.all;
package can_fd_frame_format is
------------------------------------------------------------------------------
-- Common types
------------------------------------------------------------------------------
type t_reg_type is (
reg_none,
reg_write_only,
reg_read_only,
reg_read_write,
reg_read_write_once
);
type t_memory_reg is record
address : std_logic_vector(11 downto 0);
size : integer;
reg_type : t_reg_type;
reset_val : std_logic_vector(31 downto 0);
is_implem : std_logic_vector(31 downto 0);
end record;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Address block: CAN_FD_Frame_format
......@@ -84,51 +64,6 @@ package can_fd_frame_format is
constant DATA_5_8_W_ADR : std_logic_vector(11 downto 0) := x"014";
constant DATA_61_64_W_ADR : std_logic_vector(11 downto 0) := x"04C";
------------------------------------------------------------------------------
-- Register list
------------------------------------------------------------------------------
type t_CAN_FD_Frame_format_list is array (0 to 6) of t_memory_reg;
constant CAN_FD_Frame_format_list : t_CAN_FD_Frame_format_list :=(
(address => FRAME_FORM_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000001111111011101111"),
(address => IDENTIFIER_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => TIMESTAMP_L_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => TIMESTAMP_U_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => DATA_1_4_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => DATA_5_8_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => DATA_61_64_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111")
);
------------------------------------------------------------------------------
-- FRAME_FORM_W register
--
......
......@@ -49,26 +49,6 @@ use ieee.std_logic_1164.all;
package can_fd_register_map is
------------------------------------------------------------------------------
-- Common types
------------------------------------------------------------------------------
type t_reg_type is (
reg_none,
reg_write_only,
reg_read_only,
reg_read_write,
reg_read_write_once
);
type t_memory_reg is record
address : std_logic_vector(11 downto 0);
size : integer;
reg_type : t_reg_type;
reset_val : std_logic_vector(31 downto 0);
is_implem : std_logic_vector(31 downto 0);
end record;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Address block: Control_registers
......@@ -126,261 +106,6 @@ package can_fd_register_map is
constant TIMESTAMP_LOW_ADR : std_logic_vector(11 downto 0) := x"094";
constant TIMESTAMP_HIGH_ADR : std_logic_vector(11 downto 0) := x"098";
------------------------------------------------------------------------------
-- Register list
------------------------------------------------------------------------------
type t_Control_registers_list is array (0 to 48) of t_memory_reg;
constant Control_registers_list : t_Control_registers_list :=(
(address => DEVICE_ID_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000001100101011111101",
is_implem => "00000000000000001111111111111111"),
(address => VERSION_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000000000000000"),
(address => MODE_ADR,
size => 16,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000010000",
is_implem => "00000000000000000000000110011111"),
(address => SETTINGS_ADR,
size => 16,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000000000000000"),
(address => STATUS_ADR,
size => 32,
reg_type => reg_read_only,
reset_val => "00000000000000000000000010000100",
is_implem => "00000000000000000000000011111111"),
(address => COMMAND_ADR,
size => 32,
reg_type => reg_write_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000000001111100"),
(address => INT_STAT_ADR,
size => 16,
reg_type => reg_read_write_once,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000111111111111"),
(address => INT_ENA_SET_ADR,
size => 16,
reg_type => reg_read_write_once,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000111111111111"),
(address => INT_ENA_CLR_ADR,
size => 16,
reg_type => reg_write_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000111111111111"),
(address => INT_MASK_SET_ADR,
size => 16,
reg_type => reg_read_write_once,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000111111111111"),
(address => INT_MASK_CLR_ADR,
size => 16,
reg_type => reg_write_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000111111111111"),
(address => BTR_ADR,
size => 32,
reg_type => reg_read_write,
reset_val => "00010000010100001010000110000101",
is_implem => "11111111111111111111111111111111"),
(address => BTR_FD_ADR,
size => 32,
reg_type => reg_read_write,
reset_val => "00010000001000000110000110000011",
is_implem => "11111111111110111110111110111111"),
(address => EWL_ADR,
size => 8,
reg_type => reg_read_write,
reset_val => "00000000000000000000000001100000",
is_implem => "00000000000000000000000011111111"),
(address => ERP_ADR,
size => 8,
reg_type => reg_read_write,
reset_val => "00000000000000001000000000000000",
is_implem => "00000000000000000000000000000000"),
(address => FAULT_STATE_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000010000000000000000",
is_implem => "00000000000000000000000000000000"),
(address => REC_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000000111111111"),
(address => TEC_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000000000000000"),
(address => ERR_NORM_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000001111111111111111"),
(address => ERR_FD_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000000000000000"),
(address => CTR_PRES_ADR,
size => 32,
reg_type => reg_write_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000001111111111111"),
(address => FILTER_A_MASK_ADR,
size => 32,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => FILTER_A_VAL_ADR,
size => 32,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => FILTER_B_MASK_ADR,
size => 32,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => FILTER_B_VAL_ADR,
size => 32,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => FILTER_C_MASK_ADR,
size => 32,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => FILTER_C_VAL_ADR,
size => 32,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => FILTER_RAN_LOW_ADR,
size => 32,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => FILTER_RAN_HIGH_ADR,
size => 32,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => FILTER_CONTROL_ADR,
size => 16,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000001111",
is_implem => "00000000000000001111111111111111"),
(address => FILTER_STATUS_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000000000000000"),
(address => RX_MEM_INFO_ADR,
size => 32,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111110001111111111111"),
(address => RX_POINTERS_ADR,
size => 32,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00001111111111110000111111111111"),
(address => RX_STATUS_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000001",
is_implem => "00000000000000000111111111110011"),
(address => RX_SETTINGS_ADR,
size => 8,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000000000000000"),
(address => RX_DATA_ADR,
size => 32,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => TX_STATUS_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000001000100010001000",
is_implem => "00000000000000001111111111111111"),
(address => TX_COMMAND_ADR,
size => 16,
reg_type => reg_write_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000111100000111"),
(address => TX_PRIORITY_ADR,
size => 16,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000001",
is_implem => "00000000000000000111011101110111"),
(address => ERR_CAPT_ADR,
size => 8,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000011111",
is_implem => "00000000000000000000000011111111"),
(address => ALC_ADR,
size => 8,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000000000000000"),
(address => TRV_DELAY_ADR,
size => 16,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000000000000001111111"),
(address => SSP_CFG_ADR,
size => 16,
reg_type => reg_read_write,
reset_val => "00000000000010100000000000000000",
is_implem => "00000000000000000000000000000000"),
(address => RX_FR_CTR_ADR,
size => 32,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => TX_FR_CTR_ADR,
size => 32,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => DEBUG_REGISTER_ADR,
size => 32,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000001111111111111111111"),
(address => YOLO_REG_ADR,
size => 32,
reg_type => reg_read_only,
reset_val => "11011110101011011011111011101111",
is_implem => "11111111111111111111111111111111"),
(address => TIMESTAMP_LOW_ADR,
size => 32,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => TIMESTAMP_HIGH_ADR,
size => 32,
reg_type => reg_read_only,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111")
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Address block: TX_Buffer_1
......@@ -392,31 +117,6 @@ package can_fd_register_map is
constant TXTB1_DATA_2_ADR : std_logic_vector(11 downto 0) := x"104";
constant TXTB1_DATA_20_ADR : std_logic_vector(11 downto 0) := x"14C";
------------------------------------------------------------------------------
-- Register list
------------------------------------------------------------------------------
type t_TX_Buffer_1_list is array (0 to 2) of t_memory_reg;
constant TX_Buffer_1_list : t_TX_Buffer_1_list :=(
(address => TXTB1_DATA_1_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => TXTB1_DATA_2_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => TXTB1_DATA_20_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111")
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Address block: TX_Buffer_2
......@@ -428,31 +128,6 @@ package can_fd_register_map is
constant TXTB2_DATA_2_ADR : std_logic_vector(11 downto 0) := x"204";
constant TXTB2_DATA_20_ADR : std_logic_vector(11 downto 0) := x"24C";
------------------------------------------------------------------------------
-- Register list
------------------------------------------------------------------------------
type t_TX_Buffer_2_list is array (0 to 2) of t_memory_reg;
constant TX_Buffer_2_list : t_TX_Buffer_2_list :=(
(address => TXTB2_DATA_1_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => TXTB2_DATA_2_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => TXTB2_DATA_20_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111")
);