Commit aaf55cd2 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added generics for filter support to reduce the

size further.
parent ca9fe089
......@@ -48,7 +48,14 @@ use work.ID_transfer.all;
------------------------------------------------------------------------------------------------------------
entity messageFilter is
PORT(
generic
(
constant sup_filtA :boolean := true; --Optional synthesis of received message filters
constant sup_filtB :boolean := true; -- By default the behaviour is as if all the filters are present
constant sup_filtC :boolean := true;
constant sup_range :boolean := true
);
port(
----------
--INPUTS--
----------
......@@ -142,6 +149,7 @@ begin
"0000" when others;
--Filter A input frame type filtering
gen_filtA_pos: if (sup_filtA=true) generate
int_filter_A_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_A_mask) =
(drv_filter_A_bits AND drv_filter_A_mask)
......@@ -152,8 +160,15 @@ begin
)
)
else '0';
end generate;
gen_filtA_neg: if (sup_filtA=false) generate
int_filter_A_valid <= '0';
end generate;
--Filter B input frame type filtering
gen_filtB_pos: if (sup_filtB=true) generate
int_filter_B_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_B_mask) =
(drv_filter_B_bits AND drv_filter_B_mask)
......@@ -164,8 +179,15 @@ begin
)
)
else '0';
end generate;
gen_filtB_neg: if (sup_filtB=false) generate
int_filter_B_valid <= '0';
end generate;
--Filter C input frame type filtering
gen_filtC_pos: if (sup_filtC=true) generate
int_filter_C_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_C_mask) =
(drv_filter_C_bits AND drv_filter_C_mask)
......@@ -176,8 +198,14 @@ begin
)
)
else '0';
end generate;
gen_filtC_neg: if (sup_filtC=false) generate
int_filter_C_valid <= '0';
end generate;
--Range filter for identifiers
gen_filtRan_pos: if (sup_range=true) generate
ID_reg_to_decimal(rec_ident_in,rec_ident_dec);
int_filter_ran_valid <= '1' when ( --Identifier matches the range set
( rec_ident_dec<=to_integer(unsigned(drv_filter_ran_hi_th)) )
......@@ -189,6 +217,11 @@ begin
not((drv_filter_ran_ctrl AND int_data_type)="0000")
)
else '0';
end generate;
gen_filtRan_neg: if (sup_range=false) generate
int_filter_ran_valid <= '0';
end generate;
--If received message is valid and at least one of
......@@ -204,7 +237,6 @@ begin
else rec_ident_valid;
---------------------------------------------------
--To avoid long combinational paths, valid filter
-- output is pipelined. This is OK since received
......
......@@ -62,7 +62,11 @@ entity CAN_top_level is
--Dont turn off unless external synchronisation chain is put on input of FPGA by
--synthetiser
constant ID : natural range 0 to 15:=1; --ID (bits 19-16 of adress)
constant logger_size : natural --range 0 to 512:=8
constant sup_filtA : boolean := true; --Optional synthesis of received message filters
constant sup_filtB : boolean := true; -- By default the behaviour is as if all the filters are present
constant sup_filtC : boolean := true;
constant sup_range : boolean := true;
constant logger_size : natural range 0 to 512:=8
);
port(
--------------------------
......@@ -262,6 +266,10 @@ begin
generic map(
compType => CAN_COMPONENT_TYPE,
use_logger => use_logger,
sup_filtA => sup_filtA,
sup_filtB => sup_filtB,
sup_filtC => sup_filtC,
sup_range => sup_range,
ID => ID
)
port map(
......@@ -388,6 +396,12 @@ begin
);
mes_filt_comp:messageFilter
generic map(
sup_filtA => sup_filtA,
sup_filtB => sup_filtB,
sup_filtC => sup_filtC,
sup_range => sup_range
)
port map(
clk_sys => clk_sys,
res_n => res_n,
......
......@@ -57,6 +57,10 @@ package CANcomponents is
--Dont turn off unless external synchronisation chain is put on input of FPGA by
--synthetiser
constant ID :natural range 0 to 15:=1; --ID (bits 19-16 of adress)
constant sup_filtA :boolean := true; --Optional synthesis of received message filters
constant sup_filtB :boolean := true; -- By default the behaviour is as if all the filters are present
constant sup_filtC :boolean := true;
constant sup_range :boolean := true;
constant logger_size :natural --range 0 to 512:=8
);
port(
......@@ -90,6 +94,10 @@ package CANcomponents is
generic(
constant compType : std_logic_vector(3 downto 0):= CAN_COMPONENT_TYPE;
constant use_logger : boolean := true; --Whenever event logger is present
constant sup_filtA : boolean := true; --Optional synthesis of received message filters
constant sup_filtB : boolean := true; -- By default the behaviour is as if all the filters are present
constant sup_filtC : boolean := true;
constant sup_range : boolean := true;
constant ID : natural --ID of the component
);
port(
......@@ -277,6 +285,13 @@ package CANcomponents is
--Message filter module--
-------------------------
component messageFilter is
generic
(
constant sup_filtA :boolean := true; --Optional synthesis of received message filters
constant sup_filtB :boolean := true; -- By default the behaviour is as if all the filters are present
constant sup_filtC :boolean := true;
constant sup_range :boolean := true
);
PORT(
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async reset
......
......@@ -82,6 +82,10 @@ entity registers is
generic(
constant compType :std_logic_vector(3 downto 0) := CAN_COMPONENT_TYPE;
constant use_logger :boolean := true; --Whenever event logger is present
constant sup_filtA :boolean := true; --Optional synthesis of received message filters
constant sup_filtB :boolean := true; -- By default the behaviour is as if all the filters are present
constant sup_filtC :boolean := true;
constant sup_range :boolean := true;
constant ID :natural := 1 --ID of the component
);
port(
......@@ -394,18 +398,29 @@ architecture rtl of registers is
erp <= std_logic_vector(to_unsigned(128,erp'length));
--Message filters
if (sup_filtA = true) then
filter_A_mask <= (OTHERS=>'0');
filter_B_mask <= (OTHERS=>'0');
filter_C_mask <= (OTHERS=>'0');
filter_A_value <= (OTHERS=>'0');
filter_A_ctrl <= (OTHERS=>'1'); --Only filter A is enabled to pass all message types with any identifier
end if;
if (sup_filtB = true) then
filter_B_mask <= (OTHERS=>'0');
filter_B_value <= (OTHERS=>'0');
filter_B_ctrl <= (OTHERS=>'0');
end if;
if (sup_filtB = true) then
filter_C_mask <= (OTHERS=>'0');
filter_C_value <= (OTHERS=>'0');
filter_C_ctrl <= (OTHERS=>'0');
end if;
if (sup_range = true) then
filter_ran_low <= (OTHERS=>'0');
filter_ran_high <= (OTHERS=>'0');
filter_A_ctrl <= (OTHERS=>'1'); --Only filter A is enabled to pass all message types with any identifier
filter_B_ctrl <= (OTHERS=>'0');
filter_C_ctrl <= (OTHERS=>'0');
filter_ran_ctrl <= (OTHERS=>'0');
end if;
txt1_arbit_allow <= FORBID_BUFFER;
txt2_arbit_allow <= FORBID_BUFFER;
......@@ -514,18 +529,31 @@ begin
else
--Internal registers holding its value
--Message filters
if (sup_filtA = true) then
filter_A_mask <= filter_A_mask;
filter_B_mask <= filter_B_mask;
filter_C_mask <= filter_C_mask;
filter_A_value <= filter_A_value;
filter_A_ctrl <= filter_A_ctrl;
end if;
if (sup_filtB = true) then
filter_B_mask <= filter_B_mask;
filter_B_value <= filter_B_value;
filter_B_ctrl <= filter_B_ctrl;
end if;
if (sup_filtB = true) then
filter_C_mask <= filter_C_mask;
filter_C_value <= filter_C_value;
filter_C_ctrl <= filter_C_ctrl;
end if;
if (sup_range = true) then
filter_ran_low <= filter_ran_low;
filter_ran_high <= filter_ran_high;
filter_A_ctrl <= filter_A_ctrl;
filter_B_ctrl <= filter_B_ctrl;
filter_C_ctrl <= filter_C_ctrl;
filter_ran_ctrl <= filter_ran_ctrl;
end if;
int_ena_reg <= int_ena_reg;
retr_lim_ena <= retr_lim_ena;
......@@ -661,19 +689,51 @@ begin
----------------------------------------------------
--Acceptance filters
----------------------------------------------------
when FILTER_A_VAL_ADR => filter_A_mask <= data_in(28 downto 0);
when FILTER_A_MASK_ADR => filter_A_value <= data_in(28 downto 0);
when FILTER_B_VAL_ADR => filter_B_mask <= data_in(28 downto 0);
when FILTER_B_MASK_ADR => filter_B_value <= data_in(28 downto 0);
when FILTER_C_VAL_ADR => filter_C_mask <= data_in(28 downto 0);
when FILTER_C_MASK_ADR => filter_C_value <= data_in(28 downto 0);
when FILTER_RAN_LOW_ADR => filter_ran_low <= data_in(28 downto 0);
when FILTER_RAN_HIGH_ADR => filter_ran_high <= data_in(28 downto 0);
when FILTER_A_VAL_ADR =>
if (sup_filtA = true) then
filter_A_mask <= data_in(28 downto 0);
end if;
when FILTER_A_MASK_ADR =>
if (sup_filtA = true) then
filter_A_value <= data_in(28 downto 0);
end if;
when FILTER_B_VAL_ADR =>
if (sup_filtB = true) then
filter_B_mask <= data_in(28 downto 0);
end if;
when FILTER_B_MASK_ADR =>
if (sup_filtB = true) then
filter_B_value <= data_in(28 downto 0);
end if;
when FILTER_C_VAL_ADR =>
if (sup_filtC = true) then
filter_C_mask <= data_in(28 downto 0);
end if;
when FILTER_C_MASK_ADR =>
if (sup_filtC = true) then
filter_C_value <= data_in(28 downto 0);
end if;
when FILTER_RAN_LOW_ADR =>
if (sup_range = true) then
filter_ran_low <= data_in(28 downto 0);
end if;
when FILTER_RAN_HIGH_ADR =>
if (sup_range = true) then
filter_ran_high <= data_in(28 downto 0);
end if;
when FILTER_CONTROL_ADR =>
if (sup_filtA = true) then
filter_A_ctrl <= data_in(3 downto 0);
end if;
if (sup_filtB = true) then
filter_B_ctrl <= data_in(7 downto 4);
end if;
if (sup_filtC = true) then
filter_C_ctrl <= data_in(11 downto 8);
end if;
if (sup_range = true) then
filter_ran_ctrl <= data_in(15 downto 12);
end if;
----------------------------------------------------
--TX Settings register
......@@ -836,29 +896,61 @@ begin
--Acceptance filters
----------------------------------------------------------
when FILTER_A_VAL_ADR =>
if (sup_filtA = true) then
data_out(28 downto 0) <= filter_A_mask;
data_out(31 downto 29) <= (OTHERS=>'0');
else
data_out <= (OTHERS => '0');
end if;
when FILTER_A_MASK_ADR =>
if (sup_filtA = true) then
data_out(28 downto 0) <= filter_A_value;
data_out(31 downto 29) <= (OTHERS=>'0');
else
data_out <= (OTHERS => '0');
end if;
when FILTER_B_VAL_ADR =>
if (sup_filtB = true) then
data_out(28 downto 0) <= filter_B_mask;
data_out(31 downto 29) <= (OTHERS=>'0');
else
data_out <= (OTHERS => '0');
end if;
when FILTER_B_MASK_ADR =>
if (sup_filtB = true) then
data_out(28 downto 0) <= filter_B_value;
data_out(31 downto 29) <= (OTHERS=>'0');
else
data_out <= (OTHERS => '0');
end if;
when FILTER_C_VAL_ADR =>
if (sup_filtC = true) then
data_out(28 downto 0) <= filter_C_mask;
data_out(31 downto 29) <= (OTHERS=>'0');
else
data_out <= (OTHERS => '0');
end if;
when FILTER_C_MASK_ADR =>
if (sup_filtC = true) then
data_out(28 downto 0) <= filter_C_value;
data_out(31 downto 29) <= (OTHERS=>'0');
else
data_out <= (OTHERS => '0');
end if;
when FILTER_RAN_LOW_ADR =>
if (sup_range = true) then
data_out(28 downto 0) <= filter_ran_low;
data_out(31 downto 29) <= (OTHERS=>'0');
else
data_out <= (OTHERS => '0');
end if;
when FILTER_RAN_HIGH_ADR =>
if (sup_range = true) then
data_out(28 downto 0) <= filter_ran_high;
data_out(31 downto 29) <= (OTHERS=>'0');
else
data_out <= (OTHERS => '0');
end if;
-------------------------------------------------------
--Acceptance filter configuration register
......
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