Commit a9c3d0f8 authored by Martin Jeřábek's avatar Martin Jeřábek
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readme: convert to markdown, include build & coverage status

parent a343c47b
CAN FD IP Core
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# CAN FD IP Core
[![pipeline status](https://gitlab.fel.cvut.cz/illeondr/CAN_FD_IP_Core/badges/master/pipeline.svg)](https://gitlab.fel.cvut.cz/illeondr/CAN_FD_IP_Core/commits/master)
[![coverage report](https://gitlab.fel.cvut.cz/illeondr/CAN_FD_IP_Core/badges/master/coverage.svg)](https://gitlab.fel.cvut.cz/illeondr/CAN_FD_IP_Core/commits/master)
This is repository of CAN FD IP Core written in VHDL, originally developed at
Czech Technical University - Faculty of Electrical Engineering - Department
Czech Technical University -- Faculty of Electrical Engineering -- Department
of Measurement.
The Core supports ISO and NON-ISO versions of the protocol for synthesis into
FPGAs. Core contains test framework written in VHDL and run with TCL scripts
in Modelsim Altera (or Intel) edition.
Ondrej Ille
\ No newline at end of file
Ondrej Ille
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