Commit a7b00177 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

1. Consolidated random number library.

2. Added "_s" suffix on random functions with signal output.
3. Repaired tests to call new functions.
4. Added exponential distribution.
parent c6ba9ca2
......@@ -37,7 +37,8 @@
--------------------------------------------------------------------------------
-- Purpose:
-- Package with the pseudo random number functions.
-- Package with the pseudo random number functions. Functions with postix
-- "_v" return variables, functions with postfix "_s" return signals.
--
-- For simulation only.
--
......@@ -139,7 +140,7 @@ package randomLib is
-- refresh If signal change should be processed by simulator by
-- executing: "wait for 0 ns"
----------------------------------------------------------------------------
procedure rand_real(
procedure rand_real_s(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal retval : out real;
constant refresh : in boolean := true
......@@ -169,7 +170,7 @@ package randomLib is
-- refresh If signal change should be processed by simulator by
-- executing: "wait for 0 ns"
----------------------------------------------------------------------------
procedure rand_int(
procedure rand_int_s(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
constant max : in positive;
signal retval : out natural;
......@@ -204,7 +205,7 @@ package randomLib is
-- refresh If signal change should be processed by simulator by
-- executing: "wait for 0 ns"
----------------------------------------------------------------------------
procedure rand_logic(
procedure rand_logic_s(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal retval : out std_logic;
constant chances : in real;
......@@ -240,7 +241,7 @@ package randomLib is
-- refresh If signal change should be processed by simulator by
-- executing: "wait for 0 ns"
----------------------------------------------------------------------------
procedure rand_logic_vect(
procedure rand_logic_vect_s(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal retVal : out std_logic_vector;
constant chances : in real;
......@@ -278,7 +279,7 @@ package randomLib is
-- refresh If signal change should be processed by simulator by
-- executing: "wait for 0 ns"
----------------------------------------------------------------------------
procedure rand_logic_vect_bt(
procedure rand_logic_vect_bt_s(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal retVal : inout std_logic_vector;
constant bt : in integer;
......@@ -1107,7 +1108,7 @@ end package;
package body randomLib is
procedure rand_real(
procedure rand_real_s(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal retval : out real;
constant refresh : in boolean := true
......@@ -1141,7 +1142,7 @@ package body randomLib is
end procedure;
procedure rand_int(
procedure rand_int_s(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
constant max : in positive;
signal retval : out natural;
......@@ -1182,7 +1183,7 @@ package body randomLib is
end procedure;
procedure rand_logic(
procedure rand_logic_s(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal retval : out std_logic;
constant chances : in real;
......@@ -1230,7 +1231,7 @@ package body randomLib is
procedure rand_logic_vect(
procedure rand_logic_vect_s(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal retVal : out std_logic_vector;
constant chances : in real;
......@@ -1286,7 +1287,7 @@ package body randomLib is
end procedure;
procedure rand_logic_vect_bt(
procedure rand_logic_vect_bt_s(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal retVal : inout std_logic_vector;
constant bt : in integer;
......
......@@ -191,13 +191,13 @@ begin
rx_trig = '0' and err_data = '0') then
if (rand_val > 0.95) then
rand_logic(rand_set_ctr, bs_enable, 0.9);
rand_logic_s(rand_set_ctr, bs_enable, 0.9);
wait for 0 ns;
bd_enable <= bs_enable;
rand_logic(rand_set_ctr, fixed_stuff, 0.25);
rand_logic_s(rand_set_ctr, fixed_stuff, 0.25);
rand_logic_vect(rand_set_ctr, bs_length, 0.2);
rand_logic_vect_s(rand_set_ctr, bs_length, 0.2);
wait for 0 ns;
-- Bit Stuffing of 0,1 or 2 is not needed.
......@@ -220,7 +220,7 @@ begin
begin
wait until rising_edge(tx_trig) and data_halt = '0' and
stuff_error = '0' and err_data = '0';
rand_logic(rand_tx_ctr, tx_data, 0.5);
rand_logic_s(rand_tx_ctr, tx_data, 0.5);
end process;
--------------------------------
......
......@@ -211,7 +211,7 @@ begin
if (generate_ones = true) then
data_tx <= RECESSIVE;
else
rand_logic(rand_ctr_data_gen, data_tx, 0.5);
rand_logic_s(rand_ctr_data_gen, data_tx, 0.5);
end if;
end process;
......
......@@ -320,7 +320,7 @@ begin
log("Starting loop nr " & integer'image(loop_ctr), info_l, log_level);
--Generate random ISO, non ISO
rand_logic(rand_ctr, drv_fd_type, 0.5);
rand_logic_s(rand_ctr, drv_fd_type, 0.5);
--Generate bit sequence
log("Generating random bit sequence", info_l, log_level);
......
......@@ -203,7 +203,7 @@ begin
variable rand_val:real:=0.0;
begin
wait until falling_edge(clk_sys);
rand_logic_vect(rand_ctr_2,stat_bus_short,0.1);
rand_logic_vect_s(rand_ctr_2,stat_bus_short,0.1);
--Here we emulate frame
......@@ -227,8 +227,8 @@ begin
PC_State <= sof;
end if;
rand_logic(rand_ctr_2,data_overrun,0.2);
rand_logic(rand_ctr_2,sync_edge,0.2);
rand_logic_s(rand_ctr_2,data_overrun,0.2);
rand_logic_s(rand_ctr_2,sync_edge,0.2);
rand_real_v(rand_ctr_2,rand_val);
wt:= integer(rand_val*100.0) * 1 ns;
......
......@@ -199,81 +199,81 @@ architecture int_man_unit_test of CAN_test is
)is
begin
if (error_valid = '1') then
rand_logic(rand_ctr, error_valid, 0.85);
rand_logic_s(rand_ctr, error_valid, 0.85);
else
rand_logic(rand_ctr, error_valid, 0.1);
rand_logic_s(rand_ctr, error_valid, 0.1);
end if;
if (error_passive_changed = '1') then
rand_logic(rand_ctr, error_passive_changed, 0.85);
rand_logic_s(rand_ctr, error_passive_changed, 0.85);
else
rand_logic(rand_ctr, error_passive_changed, 0.05);
rand_logic_s(rand_ctr, error_passive_changed, 0.05);
end if;
if (error_warning_limit = '1') then
rand_logic(rand_ctr, error_warning_limit, 0.85);
rand_logic_s(rand_ctr, error_warning_limit, 0.85);
else
rand_logic(rand_ctr, error_warning_limit, 0.05);
rand_logic_s(rand_ctr, error_warning_limit, 0.05);
end if;
if (arbitration_lost = '1') then
rand_logic(rand_ctr, arbitration_lost, 0.95);
rand_logic_s(rand_ctr, arbitration_lost, 0.95);
else
rand_logic(rand_ctr, arbitration_lost, 0.05);
rand_logic_s(rand_ctr, arbitration_lost, 0.05);
end if;
if (tx_finished = '1') then
rand_logic(rand_ctr, tx_finished, 0.95);
rand_logic_s(rand_ctr, tx_finished, 0.95);
else
rand_logic(rand_ctr, tx_finished, 0.05);
rand_logic_s(rand_ctr, tx_finished, 0.05);
end if;
if (br_shifted = '1') then
rand_logic(rand_ctr, br_shifted, 0.95);
rand_logic_s(rand_ctr, br_shifted, 0.95);
else
rand_logic(rand_ctr, br_shifted, 0.05);
rand_logic_s(rand_ctr, br_shifted, 0.05);
end if;
if (rx_message_disc = '1') then
rand_logic(rand_ctr, rx_message_disc, 0.95);
rand_logic_s(rand_ctr, rx_message_disc, 0.95);
else
rand_logic(rand_ctr, rx_message_disc, 0.05);
rand_logic_s(rand_ctr, rx_message_disc, 0.05);
end if;
if (rec_message_valid = '1') then
rand_logic(rand_ctr, rec_message_valid, 0.95);
rand_logic_s(rand_ctr, rec_message_valid, 0.95);
else
rand_logic(rand_ctr, rec_message_valid, 0.05);
rand_logic_s(rand_ctr, rec_message_valid, 0.05);
end if;
if (rx_full = '1') then
rand_logic(rand_ctr, rx_full, 0.95);
rand_logic_s(rand_ctr, rx_full, 0.95);
else
rand_logic(rand_ctr, rx_full, 0.05);
rand_logic_s(rand_ctr, rx_full, 0.05);
end if;
if (loger_finished = '1') then
rand_logic(rand_ctr, loger_finished, 0.95);
rand_logic_s(rand_ctr, loger_finished, 0.95);
else
rand_logic(rand_ctr, loger_finished, 0.05);
rand_logic_s(rand_ctr, loger_finished, 0.05);
end if;
if (rx_empty = '0') then
rand_logic(rand_ctr, rx_empty, 0.95);
rand_logic_s(rand_ctr, rx_empty, 0.95);
else
rand_logic(rand_ctr, rx_empty, 0.05);
rand_logic_s(rand_ctr, rx_empty, 0.05);
end if;
if (txt_hw_cmd.lock = '1') then
rand_logic(rand_ctr, txt_hw_cmd.lock, 0.95);
rand_logic_s(rand_ctr, txt_hw_cmd.lock, 0.95);
else
rand_logic(rand_ctr, txt_hw_cmd.lock, 0.05);
rand_logic_s(rand_ctr, txt_hw_cmd.lock, 0.05);
end if;
if (txt_hw_cmd.lock = '1') then
rand_logic(rand_ctr, txt_hw_cmd.unlock, 0.95);
rand_logic_s(rand_ctr, txt_hw_cmd.unlock, 0.95);
else
rand_logic(rand_ctr, txt_hw_cmd.unlock, 0.05);
rand_logic_s(rand_ctr, txt_hw_cmd.unlock, 0.05);
end if;
end procedure;
......@@ -305,19 +305,19 @@ architecture int_man_unit_test of CAN_test is
-- Only one command is generated at any time, since commands are
-- coming from different registers!
if (tmp < 0.2) then
rand_logic_vect(rand_ctr, drv_int_clear, 0.4);
rand_logic_vect_s(rand_ctr, drv_int_clear, 0.4);
elsif (tmp < 0.4) then
rand_logic_vect(rand_ctr, drv_int_ena_set, 0.2);
rand_logic_vect_s(rand_ctr, drv_int_ena_set, 0.2);
elsif (tmp < 0.6) then
rand_logic_vect(rand_ctr, drv_int_ena_clear, 0.4);
rand_logic_vect_s(rand_ctr, drv_int_ena_clear, 0.4);
elsif (tmp < 0.8) then
rand_logic_vect(rand_ctr, drv_int_mask_set, 0.2);
rand_logic_vect_s(rand_ctr, drv_int_mask_set, 0.2);
else
rand_logic_vect(rand_ctr, drv_int_mask_clear, 0.4);
rand_logic_vect_s(rand_ctr, drv_int_mask_clear, 0.4);
end if;
wait for 0 ns;
......
......@@ -94,10 +94,10 @@ architecture mess_filt_unit_test of CAN_test is
signal frame_info :out mess_filter_input_type
)is
begin
rand_logic_vect (rand_ctr, frame_info.rec_ident_in ,0.5);
rand_logic (rand_ctr, frame_info.ident_type ,0.5);
rand_logic (rand_ctr, frame_info.frame_type ,0.5);
rand_logic (rand_ctr, frame_info.rec_ident_valid ,0.9);
rand_logic_vect_s (rand_ctr, frame_info.rec_ident_in ,0.5);
rand_logic_s (rand_ctr, frame_info.ident_type ,0.5);
rand_logic_s (rand_ctr, frame_info.frame_type ,0.5);
rand_logic_s (rand_ctr, frame_info.rec_ident_valid ,0.9);
end procedure;
......@@ -106,23 +106,23 @@ architecture mess_filt_unit_test of CAN_test is
signal drv_settings :inout mess_filter_drv_type
)is
begin
rand_logic_vect (rand_ctr, drv_settings.drv_filter_A_bits, 0.50);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_A_mask, 0.15);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_A_ctrl, 0.50);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_A_bits, 0.50);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_A_mask, 0.15);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_A_ctrl, 0.50);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_B_bits, 0.50);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_B_mask, 0.15);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_B_ctrl, 0.50);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_B_bits, 0.50);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_B_mask, 0.15);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_B_ctrl, 0.50);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_C_bits, 0.50);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_C_mask, 0.15);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_C_ctrl, 0.50);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_C_bits, 0.50);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_C_mask, 0.15);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_C_ctrl, 0.50);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_ran_hi_th, 0.60);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_ran_lo_th, 0.40);
rand_logic_vect (rand_ctr, drv_settings.drv_filter_ran_ctrl, 0.50);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_ran_hi_th, 0.60);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_ran_lo_th, 0.40);
rand_logic_vect_s (rand_ctr, drv_settings.drv_filter_ran_ctrl, 0.50);
rand_logic (rand_ctr, drv_settings.drv_filters_ena, 0.9);
rand_logic_s (rand_ctr, drv_settings.drv_filters_ena, 0.9);
end procedure;
......
......@@ -154,19 +154,19 @@ architecture presc_unit_test of CAN_test is
signal setting : inout presc_drv_type
) is
begin
rand_logic_vect_bt(rand_ctr, setting.drv_tq_nbt, 0, 0.2);
rand_logic_vect_bt(rand_ctr, setting.drv_tq_dbt, 0, 0.1);
rand_logic_vect_bt_s(rand_ctr, setting.drv_tq_nbt, 0, 0.2);
rand_logic_vect_bt_s(rand_ctr, setting.drv_tq_dbt, 0, 0.1);
rand_logic_vect_bt(rand_ctr, setting.drv_prs_nbt, 0, 0.4);
rand_logic_vect_bt(rand_ctr, setting.drv_ph1_nbt, 0, 0.2);
rand_logic_vect_bt_s(rand_ctr, setting.drv_prs_nbt, 0, 0.4);
rand_logic_vect_bt_s(rand_ctr, setting.drv_ph1_nbt, 0, 0.2);
rand_logic_vect_bt(rand_ctr, setting.drv_ph2_nbt, 0, 0.2);
rand_logic_vect_bt(rand_ctr, setting.drv_prs_dbt, 0, 0.3);
rand_logic_vect_bt(rand_ctr, setting.drv_ph1_dbt, 0, 0.15);
rand_logic_vect_bt(rand_ctr, setting.drv_ph2_dbt, 0, 0.15);
rand_logic_vect_bt_s(rand_ctr, setting.drv_ph2_nbt, 0, 0.2);
rand_logic_vect_bt_s(rand_ctr, setting.drv_prs_dbt, 0, 0.3);
rand_logic_vect_bt_s(rand_ctr, setting.drv_ph1_dbt, 0, 0.15);
rand_logic_vect_bt_s(rand_ctr, setting.drv_ph2_dbt, 0, 0.15);
rand_logic_vect(rand_ctr, setting.drv_sjw_nbt, 0.2);
rand_logic_vect(rand_ctr, setting.drv_sjw_dbt, 0.2);
rand_logic_vect_s(rand_ctr, setting.drv_sjw_nbt, 0.2);
rand_logic_vect_s(rand_ctr, setting.drv_sjw_dbt, 0.2);
-- Here we check that settings are matching IPT!!
-- This is stated in documentation and is up to responsible
......
......@@ -255,8 +255,8 @@ begin
-- Generate random address and data and attempt to store it
-- to the buffer.
wait until rising_edge(clk_sys);
rand_logic_vect(rand_gen_ctr, tran_data, 0.5);
rand_logic_vect(rand_gen_ctr, tran_addr, 0.5);
rand_logic_vect_s(rand_gen_ctr, tran_data, 0.5);
rand_logic_vect_s(rand_gen_ctr, tran_addr, 0.5);
if (to_integer(unsigned(tran_addr)) > 19) then
tran_addr <= "00000";
end if;
......@@ -328,8 +328,8 @@ begin
wait until falling_edge(clk_sys);
-- Generate HW commands
rand_logic(rand_com_gen_ctr, txt_hw_cmd.lock, 0.2);
rand_logic(rand_com_gen_ctr, txt_hw_cmd.unlock, 0.2);
rand_logic_s(rand_com_gen_ctr, txt_hw_cmd.lock, 0.2);
rand_logic_s(rand_com_gen_ctr, txt_hw_cmd.unlock, 0.2);
if (txtb_state /= txt_ready) then
txt_hw_cmd.lock <= '0';
......@@ -356,9 +356,9 @@ begin
end if;
-- Generate SW commands
rand_logic(rand_com_gen_ctr, txt_sw_cmd.set_rdy, 0.2);
rand_logic(rand_com_gen_ctr, txt_sw_cmd.set_ety, 0.2);
rand_logic(rand_com_gen_ctr, txt_sw_cmd.set_abt, 0.2);
rand_logic_s(rand_com_gen_ctr, txt_sw_cmd.set_rdy, 0.2);
rand_logic_s(rand_com_gen_ctr, txt_sw_cmd.set_ety, 0.2);
rand_logic_s(rand_com_gen_ctr, txt_sw_cmd.set_abt, 0.2);
wait for 0 ns;
-- Calculate the expected state
......
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