Commit a3eeb326 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

syn: Update Vivado project.

parent e2abd32d
Pipeline #13417 passed with stages
in 15 minutes and 23 seconds
......@@ -39,7 +39,7 @@
#*******************************************************************************
# Create 100 MHz clock
create_clock -name {clk_sys} -period 10.000 -waveform { 0.000 5.000 } [get_nets {clk_sys}]
create_clock -name {clk_sys} -period 10.000 -waveform { 0.000 5.000 } [get_ports {aclk}]
# Reset synchroniser attirbutes
set rst_sync_chain_1 [get_cells {*rst_sync_comp/rst_n*}]
......
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