Commit a19f4ed0 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Updated SETTINGS register indices.

parent 01be7dd4
......@@ -470,7 +470,7 @@ architecture rtl of canfd_registers is
-- Enable register
CAN_enable <= ENA_RSTVAL;
FD_type <= FD_TYPE_RSTVAL;
FD_type <= NISOFD_RSTVAL;
-- Mode register
mode_reg(RST_IND) <= RST_RSTVAL;
......@@ -482,7 +482,7 @@ architecture rtl of canfd_registers is
-- Retransmitt limit enable
retr_lim_ena <= RTRLE_RSTVAL;
retr_lim_th <= RTR_TH_RSTVAL; -- Retr. limit treshold zeroes
retr_lim_th <= RTRTH_RSTVAL; -- Retr. limit treshold zeroes
sjw_norm <= SJW_RSTVAL;
brp_norm <= BRP_RSTVAL;
......@@ -924,12 +924,12 @@ begin
--Settings register
write_be_s(retr_lim_ena, RTRLE_IND, data_in, sbe);
write_be_vect(retr_lim_th, 0, 3, data_in, RTR_TH_L,
RTR_TH_H, sbe);
write_be_s(intLoopbackEna, INT_LOOP_IND, data_in,
write_be_vect(retr_lim_th, 0, 3, data_in, RTRTH_L,
RTRTH_H, sbe);
write_be_s(intLoopbackEna, ILBP_IND, data_in,
sbe);
write_be_s(CAN_enable, ENA_IND, data_in, sbe);
write_be_s(FD_type, FD_TYPE_IND, data_in, sbe);
write_be_s(FD_type, NISOFD_IND, data_in, sbe);
--------------------------------------------------------
-- INT_STATUS register
......@@ -1216,16 +1216,16 @@ begin
data_out_int(RTRLE_IND) <=
retr_lim_ena;
data_out_int(RTR_TH_H downto RTR_TH_L) <=
data_out_int(RTRTH_H downto RTRTH_L) <=
retr_lim_th;
data_out_int(INT_LOOP_IND) <=
data_out_int(ILBP_IND) <=
intLoopbackEna;
data_out_int(ENA_IND) <=
CAN_enable;
data_out_int(FD_TYPE_IND) <=
data_out_int(NISOFD_IND) <=
FD_type;
--------------------------------------------------------
......
......@@ -2808,7 +2808,7 @@ package body CANtestLib is
else
data(RTRLE_IND) := '0';
end if;
data(RTR_TH_H downto RTR_TH_L) := std_logic_vector(to_unsigned(limit, 4));
data(RTRTH_H downto RTRTH_L) := std_logic_vector(to_unsigned(limit, 4));
CAN_write(data, MODE_ADR, ID, mem_bus);
end procedure;
......@@ -3807,15 +3807,15 @@ package body CANtestLib is
CAN_read(data, SETTINGS_ADR, ID, mem_bus, BIT_8);
if (mode.iso_fd_support) then
data(FD_TYPE_IND) := '0';
data(NISOFD_IND) := '0';
else
data(FD_TYPE_IND) := '1';
data(NISOFD_IND) := '1';
end if;
if (mode.internal_loopback) then
data(INT_LOOP_IND) := '1';
data(ILBP_IND) := '1';
else
data(INT_LOOP_IND) := '0';
data(ILBP_IND) := '0';
end if;
CAN_write(data, SETTINGS_ADR, ID, mem_bus, BIT_8);
......@@ -3874,13 +3874,13 @@ package body CANtestLib is
CAN_read(data, SETTINGS_ADR, ID, mem_bus, BIT_8);
if (data(FD_TYPE_IND) = '0') then
if (data(NISOFD_IND) = '0') then
mode.iso_fd_support := true;
else
mode.iso_fd_support := false;
end if;
if (data(INT_LOOP_IND) = '1') then
if (data(ILBP_IND) = '1') then
mode.internal_loopback := true;
else
mode.internal_loopback := false;
......@@ -3997,8 +3997,8 @@ package body CANtestLib is
data(ENA_IND) := '0';
end if;
data(RTR_TH_H downto RTR_TH_L) :=
std_logic_vector(to_unsigned(limit, RTR_TH_H - RTR_TH_L + 1));
data(RTRTH_H downto RTRTH_L) :=
std_logic_vector(to_unsigned(limit, RTRTH_H - RTRTH_L + 1));
CAN_write(data, SETTINGS_ADR, ID, mem_bus, BIT_8);
end procedure;
......
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