Commit a17be3b7 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Remove log which fires too often.

parent 39f4a898
Pipeline #9584 passed with stage
in 29 seconds
......@@ -380,8 +380,6 @@ begin
-- Assertions
------------------------------------------------------------------------------
-- psl default clock is rising_edge(clk_sys);
--
------------------------------------------------------------------------------
-- Functional coverage
......@@ -389,7 +387,6 @@ begin
--
-- psl txt_buf_wait_till_timestamp_cov : cover
-- (curr_state = s_arb_sel_upp_ts and fsm_wait_state_q = '0' and
-- timestamp_valid = '0')
-- report "TXT Buffer waiting for Timestamp to reach TX Time";
-- timestamp_valid = '0');
end architecture;
\ No newline at end of file
end architecture;
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