Commit 9ebc8ab0 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added relative includes for the original pyXact framework.

parent 0c9d92ec
# To generate register map package with register addresses and bit offset: # To generate register map package with register addresses and bit offset:
py gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --fieldMap Regs --addrMap Regs --wordWidth 32 --outFile ../src/Libraries/CAN_FD_register_map.vhd --packName CAN_FD_register_map python3.5 gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --fieldMap Regs --addrMap Regs --wordWidth 32 --outFile ../src/Libraries/CAN_FD_register_map.vhd --packName CAN_FD_register_map
# To generate frame format related constants # To generate frame format related constants
py gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --fieldMap Frame_format --addrMap Frame_format --wordWidth 32 --outFile ../src/Libraries/CAN_FD_frame_format.vhd --packName CAN_FD_frame_format python3.5 gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --fieldMap Frame_format --addrMap Frame_format --wordWidth 32 --outFile ../src/Libraries/CAN_FD_frame_format.vhd --packName CAN_FD_frame_format
# To generate C header files (register map and frame format) # To generate C header files (register map and frame format)
py gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName CAN_FD_frame_format python3.5 gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName CAN_FD_frame_format
py gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName CAN_FD_frame_format py gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName CAN_FD_frame_format
# To generate Lyx docu for register map # To generate Lyx docu for register map
py gen_lyx_docu.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap Regs --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/registerMap.lyx --chaptName "Register map" --genRegions True --genFiDesc True python3.5 gen_lyx_docu.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap Regs --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/registerMap.lyx --chaptName "Register map" --genRegions True --genFiDesc True
# To generate Lyx docu for CAN frame # To generate Lyx docu for CAN frame
py gen_lyx_docu.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap Frame_format --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/CANFrameFormat.lyx --chaptName "CAN Frame format" --genRegions False --genFiDesc True python3.5 gen_lyx_docu.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap Frame_format --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/CANFrameFormat.lyx --chaptName "CAN Frame format" --genRegions False --genFiDesc True
######################################### #########################################
## To perform complete update ## To perform complete update
######################################### #########################################
py update_reg_map.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --updVHDL True --updHeader True --updDocs True python3.5 update_reg_map.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --updVHDL True --updHeader True --updDocs True
\ No newline at end of file
...@@ -23,7 +23,7 @@ import math ...@@ -23,7 +23,7 @@ import math
################################################################################ ################################################################################
# File path to the local repo of the PyXact framework # File path to the local repo of the PyXact framework
################################################################################ ################################################################################
PYXACT_PATH = "E:\Skola\CVUT-FEL\CAN_FD_IP_Core\scripts\pyXact_generator\ipyxact_parser" PYXACT_PATH = "./pyXact_generator/ipyxact_parser"
sys.path.insert(0, PYXACT_PATH) sys.path.insert(0, PYXACT_PATH)
from ipyxact.ipyxact import Component from ipyxact.ipyxact import Component
...@@ -43,4 +43,4 @@ def str_arg_to_bool(input): ...@@ -43,4 +43,4 @@ def str_arg_to_bool(input):
input == "y"): input == "y"):
return True return True
else: else:
return False return False
\ No newline at end of file
...@@ -60,25 +60,27 @@ if __name__ == '__main__': ...@@ -60,25 +60,27 @@ if __name__ == '__main__':
print("** Generating CAN FD register map") print("** Generating CAN FD register map")
print(80 * "*") print(80 * "*")
pythonAlias = "python3.5"
if (str_arg_to_bool(args.updVHDL)): if (str_arg_to_bool(args.updVHDL)):
print("Generating CAN FD memory registers VHDL package...\n") print("Generating CAN FD memory registers VHDL package...\n")
os.system("""py gen_vhdl_package.py --licPath ../LICENSE --xactSpec {} --fieldMap Regs --addrMap Regs --wordWidth 32 --outFile ../src/Libraries/CAN_FD_register_map.vhd --packName CAN_FD_register_map""".format(args.xactSpec)) os.system("""{} gen_vhdl_package.py --licPath ../LICENSE --xactSpec {} --fieldMap Regs --addrMap Regs --wordWidth 32 --outFile ../src/Libraries/CAN_FD_register_map.vhd --packName CAN_FD_register_map""".format(pythonAlias, args.xactSpec))
os.system("""py gen_vhdl_package.py --licPath ../LICENSE --xactSpec {} --fieldMap Frame_format --addrMap Frame_format --wordWidth 32 --outFile ../src/Libraries/CAN_FD_frame_format.vhd --packName CAN_FD_frame_format""".format(args.xactSpec)) os.system("""{} gen_vhdl_package.py --licPath ../LICENSE --xactSpec {} --fieldMap Frame_format --addrMap Frame_format --wordWidth 32 --outFile ../src/Libraries/CAN_FD_frame_format.vhd --packName CAN_FD_frame_format""".format(pythonAlias, args.xactSpec))
print("\nDone\n") print("\nDone\n")
if (str_arg_to_bool(args.updHeader)): if (str_arg_to_bool(args.updHeader)):
print("Generating CAN FD memory registers Header file...\n") print("Generating CAN FD memory registers Header file...\n")
os.system("""py gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName CAN_FD_frame_format""".format(args.xactSpec)) os.system("""{} gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName CAN_FD_frame_format""".format(pythonAlias, args.xactSpec))
os.system("""py gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName CAN_FD_frame_format""".format(args.xactSpec)) os.system("""{} gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName CAN_FD_frame_format""".format(pythonAlias, args.xactSpec))
print("\nDone\n") print("\nDone\n")
if (str_arg_to_bool(args.updDocs)): if (str_arg_to_bool(args.updDocs)):
print("Generating CAN FD memory registers Documentation...\n") print("Generating CAN FD memory registers Documentation...\n")
os.system("""py gen_lyx_docu.py --xactSpec {} --memMap Regs --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/registerMap.lyx --chaptName "Register map" --genRegions True --genFiDesc True""".format(args.xactSpec)) os.system("""{} gen_lyx_docu.py --xactSpec {} --memMap Regs --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/registerMap.lyx --chaptName "Register map" --genRegions True --genFiDesc True""".format(pythonAlias, args.xactSpec))
os.system("""py gen_lyx_docu.py --xactSpec {} --memMap Frame_format --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/CANFrameFormat.lyx --chaptName "CAN Frame format" --genRegions False --genFiDesc True""".format(args.xactSpec)) os.system("""{} gen_lyx_docu.py --xactSpec {} --memMap Frame_format --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/CANFrameFormat.lyx --chaptName "CAN Frame format" --genRegions False --genFiDesc True""".format(pythonAlias, args.xactSpec))
print("\nDone\n") print("\nDone\n")
print( 80 * "*") print( 80 * "*")
print("** Finished") print("** Finished")
print(80 * "*") print(80 * "*")
\ No newline at end of file
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