Commit 9cc67c0c authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

src: Use {} brackets for PSL cover entries.

parent 6743049f
......@@ -1238,38 +1238,38 @@ begin
-- Transmitted frame combinations (no RTR)
-- psl tx_base_id_can_2_0_cov : cover
-- (tran_ident_type = BASE and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '0');
-- {tran_ident_type = BASE and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '0'};
-- psl tx_extended_id_can_2_0_cov : cover
-- (tran_ident_type = EXTENDED and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '0');
-- {tran_ident_type = EXTENDED and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '0'};
-- psl tx_base_id_can_fd_cov : cover
-- (tran_ident_type = BASE and tran_frame_type = FD_CAN and
-- tran_is_rtr = '0');
-- {tran_ident_type = BASE and tran_frame_type = FD_CAN and
-- tran_is_rtr = '0'};
-- psl tx_extended_id_can_fd_cov : cover
-- (tran_ident_type = EXTENDED and tran_frame_type = FD_CAN and
-- tran_is_rtr = '0');
-- {tran_ident_type = EXTENDED and tran_frame_type = FD_CAN and
-- tran_is_rtr = '0'};
-- RTR frames (in combination with FD_CAN, this is ignored!)
-- psl tx_base_id_can_2_0_rtr_cov : cover
-- (tran_ident_type = BASE and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '1');
-- {tran_ident_type = BASE and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '1'};
-- psl tx_extended_id_can_2_0_rtr_cov : cover
-- (tran_ident_type = EXTENDED and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '1');
-- {tran_ident_type = EXTENDED and tran_frame_type = NORMAL_CAN and
-- tran_is_rtr = '1'};
-- psl tx_base_id_can_fd_rtr_cov : cover
-- (tran_ident_type = BASE and tran_frame_type = FD_CAN and
-- tran_is_rtr = '1');
-- {tran_ident_type = BASE and tran_frame_type = FD_CAN and
-- tran_is_rtr = '1'};
-- psl tx_extended_id_can_fd_rtr_cov : cover
-- (tran_ident_type = EXTENDED and tran_frame_type = FD_CAN and
-- tran_is_rtr = '1');
-- {tran_ident_type = EXTENDED and tran_frame_type = FD_CAN and
-- tran_is_rtr = '1'};
-- <RELEASE_ON>
......
......@@ -2967,88 +2967,88 @@ begin
-- Error frame request in various parts of CAN frame!
-- psl err_frm_req_in_sof_cov : cover
-- (curr_state = s_pc_sof and err_frm_req);
-- {curr_state = s_pc_sof and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_base_id_in_base_cov : cover
-- (curr_state = s_pc_base_id and err_frm_req);
-- {curr_state = s_pc_base_id and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ext_id_in_ext_id_cov : cover
-- (curr_state = s_pc_ext_id and err_frm_req);
-- {curr_state = s_pc_ext_id and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ext_id_in_rtr_srr_r1_cov : cover
-- (curr_state = s_pc_rtr_srr_r1 and err_frm_req);
-- {curr_state = s_pc_rtr_srr_r1 and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ext_id_in_ide_cov : cover
-- (curr_state = s_pc_ide and err_frm_req);
-- {curr_state = s_pc_ide and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_rtr_r1_cov : cover
-- (curr_state = s_pc_rtr_r1 and err_frm_req);
-- {curr_state = s_pc_rtr_r1 and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_edl_r1_cov : cover
-- (curr_state = s_pc_edl_r1 and err_frm_req);
-- {curr_state = s_pc_edl_r1 and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_r0_ext_cov : cover
-- (curr_state = s_pc_r0_ext and err_frm_req);
-- {curr_state = s_pc_r0_ext and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_r0_fd_cov : cover
-- (curr_state = s_pc_r0_fd and err_frm_req);
-- {curr_state = s_pc_r0_fd and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_edl_r0_cov : cover
-- (curr_state = s_pc_edl_r0 and err_frm_req);
-- {curr_state = s_pc_edl_r0 and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_esi_cov : cover
-- (curr_state = s_pc_esi and err_frm_req);
-- {curr_state = s_pc_esi and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_dlc_cov : cover
-- (curr_state = s_pc_dlc and err_frm_req);
-- {curr_state = s_pc_dlc and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_data_cov : cover
-- (curr_state = s_pc_data and err_frm_req);
-- {curr_state = s_pc_data and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_stuff_count_cov : cover
-- (curr_state = s_pc_stuff_count and err_frm_req);
-- {curr_state = s_pc_stuff_count and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_crc_cov : cover
-- (curr_state = s_pc_crc and err_frm_req);
-- {curr_state = s_pc_crc and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_crc_delim_cov : cover
-- (curr_state = s_pc_crc_delim and err_frm_req);
-- {curr_state = s_pc_crc_delim and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ack_cov : cover
-- (curr_state = s_pc_ack and err_frm_req);
-- {curr_state = s_pc_ack and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_eof_cov : cover
-- (curr_state = s_pc_eof and err_frm_req);
-- {curr_state = s_pc_eof and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_act_err_flag_cov : cover
-- (curr_state = s_pc_act_err_flag and err_frm_req);
-- {curr_state = s_pc_act_err_flag and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_pas_err_flag_cov : cover
-- (curr_state = s_pc_pas_err_flag and err_frm_req);
-- {curr_state = s_pc_pas_err_flag and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ovr_flag_cov : cover
-- (curr_state = s_pc_ovr_flag and err_frm_req);
-- {curr_state = s_pc_ovr_flag and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_ovr_delim_cov : cover
-- (curr_state = s_pc_ovr_delim and err_frm_req);
-- {curr_state = s_pc_ovr_delim and err_frm_req = '1'};
-- psl err_frm_req_in_s_pc_err_delim_cov : cover
-- (curr_state = s_pc_err_delim and err_frm_req);
-- {curr_state = s_pc_err_delim and err_frm_req = '1'};
-- Overload frame requests
-- psl ovr_from_eof_cov : cover
-- (curr_state = s_pc_eof and next_state = s_pc_ovr_flag);
-- {curr_state = s_pc_eof and next_state = s_pc_ovr_flag};
-- psl ovr_from_intermission_cov : cover
-- (curr_state = s_pc_intermission and next_state = s_pc_ovr_flag);
-- {curr_state = s_pc_intermission and next_state = s_pc_ovr_flag};
-- psl ovr_from_err_delim : cover
-- (curr_state = s_pc_err_delim and next_state = s_pc_ovr_flag);
-- {curr_state = s_pc_err_delim and next_state = s_pc_ovr_flag};
-- psl ovr_from_ovr_delim_cov : cover
-- (curr_state = s_pc_ovr_delim and next_state = s_pc_ovr_flag);
-- {curr_state = s_pc_ovr_delim and next_state = s_pc_ovr_flag};
-- <RELEASE_ON>
......
......@@ -300,84 +300,84 @@ begin
-- {int_vect_i(RXI_IND) = '0';int_vect_i(RXI_IND) = '1'};
-- psl rxi_enable_cov : cover
-- (int_vect_i(RXI_IND) = '1' and int_ena(RXI_IND) = '1');
-- {int_vect_i(RXI_IND) = '1' and int_ena(RXI_IND) = '1'};
-- psl txi_set_cov : cover
-- {int_vect_i(TXI_IND) = '0';int_vect_i(TXI_IND) = '1'};
-- psl txi_enable_cov : cover
-- (int_vect_i(TXI_IND) = '1' and int_ena(TXI_IND) = '1');
-- {int_vect_i(TXI_IND) = '1' and int_ena(TXI_IND) = '1'};
-- psl ewli_int_set_cov : cover
-- {int_vect_i(EWLI_IND) = '0';int_vect_i(EWLI_IND) = '1'};
-- psl ewli_enable_cov : cover
-- (int_vect_i(EWLI_IND) = '1' and int_ena(EWLI_IND) = '1');
-- {int_vect_i(EWLI_IND) = '1' and int_ena(EWLI_IND) = '1'};
-- psl doi_int_set_cov : cover
-- {int_vect_i(DOI_IND) = '0';int_vect_i(DOI_IND) = '1'};
-- psl doi_enable_cov : cover
-- (int_vect_i(DOI_IND) = '1' and int_ena(DOI_IND) = '1');
-- {int_vect_i(DOI_IND) = '1' and int_ena(DOI_IND) = '1'};
-- psl fcsi_int_set_cov : cover
-- {int_vect_i(FCSI_IND) = '0';int_vect_i(FCSI_IND) = '1'};
-- psl fcsi_enable_cov : cover
-- (int_vect_i(FCSI_IND) = '1' and int_ena(FCSI_IND) = '1');
-- {int_vect_i(FCSI_IND) = '1' and int_ena(FCSI_IND) = '1'};
-- psl ali_int_set_cov : cover
-- {int_vect_i(ALI_IND) = '0';int_vect_i(ALI_IND) = '1'};
-- psl ali_enable_cov : cover
-- (int_vect_i(ALI_IND) = '1' and int_ena(ALI_IND) = '1');
-- {int_vect_i(ALI_IND) = '1' and int_ena(ALI_IND) = '1'};
-- psl beu_int_set_cov : cover
-- {int_vect_i(BEI_IND) = '0';int_vect_i(BEI_IND) = '1'};
-- psl bei_enable_cov : cover
-- (int_vect_i(BEI_IND) = '1' and int_ena(BEI_IND) = '1');
-- {int_vect_i(BEI_IND) = '1' and int_ena(BEI_IND) = '1'};
-- psl rxfi_int_set_cov : cover
-- {int_vect_i(RXFI_IND) = '0';int_vect_i(RXFI_IND) = '1'};
-- psl rxfi_enable_cov : cover
-- (int_vect_i(RXFI_IND) = '1' and int_ena(RXFI_IND) = '1');
-- {int_vect_i(RXFI_IND) = '1' and int_ena(RXFI_IND) = '1'};
-- psl bsi_int_set_cov : cover
-- {int_vect_i(BSI_IND) = '0';int_vect_i(BSI_IND) = '1'};
-- psl bsi_enable_cov : cover
-- (int_vect_i(BSI_IND) = '1' and int_ena(BSI_IND) = '1');
-- {int_vect_i(BSI_IND) = '1' and int_ena(BSI_IND) = '1'};
-- psl rbnei_int_set_cov : cover
-- {int_vect_i(RBNEI_IND) = '0';int_vect_i(RBNEI_IND) = '1'};
-- psl rbnei_enable_cov : cover
-- (int_vect_i(RBNEI_IND) = '1' and int_ena(RBNEI_IND) = '1');
-- {int_vect_i(RBNEI_IND) = '1' and int_ena(RBNEI_IND) = '1'};
-- psl txbhci_int_set_cov : cover
-- {int_vect_i(TXBHCI_IND) = '0';int_vect_i(TXBHCI_IND) = '1'};
-- psl txbhci_enable_cov : cover
-- (int_vect_i(TXBHCI_IND) = '1' and int_ena(TXBHCI_IND) = '1');
-- {int_vect_i(TXBHCI_IND) = '1' and int_ena(TXBHCI_IND) = '1'};
-- psl ofi_int_set_cov : cover
-- {int_vect_i(OFI_IND) = '0';int_vect_i(OFI_IND) = '1'};
-- psl ofi_enable_cov : cover
-- (int_vect_i(OFI_IND) = '1' and int_ena(OFI_IND) = '1');
-- {int_vect_i(OFI_IND) = '1' and int_ena(OFI_IND) = '1'};
-- <RELEASE_ON>
end architecture;
\ No newline at end of file
......@@ -985,285 +985,285 @@ begin
-- PSL functional coverage
----------------------------------------------------------------------------
-- psl default clock is rising_edge(clk_sys);
-- psl device_id_read_access_cov : cover (
-- psl device_id_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(0) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl version_read_access_cov : cover (
-- psl version_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(0) = '1' and
-- (be(2) = '1' or be(3) = '1'));
-- (be(2) = '1' or be(3) = '1')};
-- psl mode_write_access_cov : cover (
-- psl mode_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(1) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl mode_read_access_cov : cover (
-- psl mode_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(1) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl settings_write_access_cov : cover (
-- psl settings_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(1) = '1' and
-- (be(2) = '1' or be(3) = '1'));
-- (be(2) = '1' or be(3) = '1')};
-- psl settings_read_access_cov : cover (
-- psl settings_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(1) = '1' and
-- (be(2) = '1' or be(3) = '1'));
-- (be(2) = '1' or be(3) = '1')};
-- psl status_read_access_cov : cover (
-- psl status_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(2) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl command_write_access_cov : cover (
-- psl command_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(3) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl int_stat_write_access_cov : cover (
-- psl int_stat_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(4) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl int_stat_read_access_cov : cover (
-- psl int_stat_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(4) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl int_ena_set_write_access_cov : cover (
-- psl int_ena_set_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(5) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl int_ena_set_read_access_cov : cover (
-- psl int_ena_set_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(5) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl int_ena_clr_write_access_cov : cover (
-- psl int_ena_clr_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(6) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl int_mask_set_write_access_cov : cover (
-- psl int_mask_set_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(7) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl int_mask_set_read_access_cov : cover (
-- psl int_mask_set_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(7) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl int_mask_clr_write_access_cov : cover (
-- psl int_mask_clr_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(8) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl btr_write_access_cov : cover (
-- psl btr_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(9) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl btr_read_access_cov : cover (
-- psl btr_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(9) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl btr_fd_write_access_cov : cover (
-- psl btr_fd_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(10) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl btr_fd_read_access_cov : cover (
-- psl btr_fd_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(10) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl ewl_write_access_cov : cover (
-- psl ewl_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(11) = '1' and
-- (be(0) = '1'));
-- (be(0) = '1')};
-- psl ewl_read_access_cov : cover (
-- psl ewl_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(11) = '1' and
-- (be(0) = '1'));
-- (be(0) = '1')};
-- psl erp_write_access_cov : cover (
-- psl erp_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(11) = '1' and
-- (be(1) = '1'));
-- (be(1) = '1')};
-- psl erp_read_access_cov : cover (
-- psl erp_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(11) = '1' and
-- (be(1) = '1'));
-- (be(1) = '1')};
-- psl fault_state_read_access_cov : cover (
-- psl fault_state_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(11) = '1' and
-- (be(2) = '1' or be(3) = '1'));
-- (be(2) = '1' or be(3) = '1')};
-- psl rec_read_access_cov : cover (
-- psl rec_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(12) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl tec_read_access_cov : cover (
-- psl tec_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(12) = '1' and
-- (be(2) = '1' or be(3) = '1'));
-- (be(2) = '1' or be(3) = '1')};
-- psl err_norm_read_access_cov : cover (
-- psl err_norm_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(13) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl err_fd_read_access_cov : cover (
-- psl err_fd_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(13) = '1' and
-- (be(2) = '1' or be(3) = '1'));
-- (be(2) = '1' or be(3) = '1')};
-- psl ctr_pres_write_access_cov : cover (
-- psl ctr_pres_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(14) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_a_mask_write_access_cov : cover (
-- psl filter_a_mask_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(15) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_a_mask_read_access_cov : cover (
-- psl filter_a_mask_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(15) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_a_val_write_access_cov : cover (
-- psl filter_a_val_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(16) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_a_val_read_access_cov : cover (
-- psl filter_a_val_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(16) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_b_mask_write_access_cov : cover (
-- psl filter_b_mask_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(17) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_b_mask_read_access_cov : cover (
-- psl filter_b_mask_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(17) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_b_val_write_access_cov : cover (
-- psl filter_b_val_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(18) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_b_val_read_access_cov : cover (
-- psl filter_b_val_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(18) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_c_mask_write_access_cov : cover (
-- psl filter_c_mask_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(19) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_c_mask_read_access_cov : cover (
-- psl filter_c_mask_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(19) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_c_val_write_access_cov : cover (
-- psl filter_c_val_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(20) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_c_val_read_access_cov : cover (
-- psl filter_c_val_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(20) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_ran_low_write_access_cov : cover (
-- psl filter_ran_low_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(21) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_ran_low_read_access_cov : cover (
-- psl filter_ran_low_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(21) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_ran_high_write_access_cov : cover (
-- psl filter_ran_high_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(22) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_ran_high_read_access_cov : cover (
-- psl filter_ran_high_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(22) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl filter_control_write_access_cov : cover (
-- psl filter_control_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(23) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl filter_control_read_access_cov : cover (
-- psl filter_control_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(23) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl filter_status_read_access_cov : cover (
-- psl filter_status_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(23) = '1' and
-- (be(2) = '1' or be(3) = '1'));
-- (be(2) = '1' or be(3) = '1')};
-- psl rx_mem_info_read_access_cov : cover (
-- psl rx_mem_info_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(24) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl rx_pointers_read_access_cov : cover (
-- psl rx_pointers_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(25) = '1' and
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1'));
-- (be(0) = '1' or be(1) = '1' or be(2) = '1' or be(3) = '1')};
-- psl rx_status_read_access_cov : cover (
-- psl rx_status_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(26) = '1' and
-- (be(0) = '1' or be(1) = '1'));
-- (be(0) = '1' or be(1) = '1')};
-- psl rx_settings_write_access_cov : cover (
-- psl rx_settings_write_access_cov : cover {
-- cs = '1' and write = '1' and reg_sel(26) = '1' and
-- (be(2) = '1'));
-- (be(2) = '1')};
-- psl rx_settings_read_access_cov : cover (
-- psl rx_settings_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(26) = '1' and
-- (be(2) = '1'));
-- (be(2) = '1')};
-- psl rx_data_read_access_cov : cover (
-- psl rx_data_read_access_cov : cover {
-- cs = '1' and read = '1' and reg_sel(27) = '1' and