Commit 9baf9f0b authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Re-generated register map. Added RXFRST and TXFCRST commands

to command register.
parent 91c6ea9f
......@@ -3895,7 +3895,7 @@ label{COMMAND
\end_inset
\end_layout
\begin_layout Description
Type: writeOnce
Type: write-only
\end_layout
\begin_layout Description
Address: 0x5
......@@ -4012,19 +4012,19 @@ Reserved\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
Reserved\end_layout
TXFCRST\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
Reserved\end_layout
RXFCRST\end_layout
 
\end_inset
</cell>
......@@ -4090,7 +4090,7 @@ Reset value\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
-\end_layout
0\end_layout
 
\end_inset
</cell>
......@@ -4098,7 +4098,7 @@ Reset value\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
-\end_layout
0\end_layout
 
\end_inset
</cell>
......@@ -4161,6 +4161,12 @@ CDO Clear data overrun flag. This command will clear data overrun flag on RX Buf
\begin_layout Description
ERCRST Error counter reset. Issuing this command will erase TX, RX error counters after 128 conecutive ocurrences of 11 recessive bits. This command can be used as protocol compliant transition from Bus-off to Error Active. Upon completion, TX RX Error counters are erased and fault confinement state is set to Error Active.
\end_layout
\begin_layout Description
RXFCRST Clear RX frames counter.
\end_layout
\begin_layout Description
TXFCRST Clear TX frames counter.
\end_layout
\begin_layout Standard
\begin_inset VSpace bigskip
\end_inset
......@@ -4761,7 +4767,7 @@ label{INT_STAT
\end_inset
\end_layout
\begin_layout Description
Type: read-write
Type: read-writeOnce
\end_layout
\begin_layout Description
Address: 0x8
......@@ -5309,7 +5315,7 @@ label{INT_ENA_SET
\end_inset
\end_layout
\begin_layout Description
Type: read-write
Type: read-writeOnce
\end_layout
\begin_layout Description
Address: 0xC
......@@ -6339,7 +6345,7 @@ label{INT_MASK_SET
\end_inset
\end_layout
\begin_layout Description
Type: read-write
Type: read-writeOnce
\end_layout
\begin_layout Description
Address: 0x14
......@@ -25437,7 +25443,7 @@ Address: 0x64
Size: 4 bytes
\end_layout
\begin_layout Standard
Read data word from RX Buffer.
\end_layout
\begin_layout Standard
\noindent
......@@ -29102,7 +29108,7 @@ label{RX_COUNTER
\end_inset
\end_layout
\begin_layout Description
Type: read-write
Type: read-only
\end_layout
\begin_layout Description
Address: 0x7C
......@@ -30103,7 +30109,7 @@ label{TX_COUNTER
\end_inset
\end_layout
\begin_layout Description
Type: read-write
Type: read-only
\end_layout
\begin_layout Description
Address: 0x80
......@@ -35018,7 +35024,7 @@ label{LOG_TRIG_CONFIG
\end_inset
\end_layout
\begin_layout Description
Type:
Type: read-write
\end_layout
\begin_layout Description
Address: 0x500
......@@ -36070,7 +36076,7 @@ label{LOG_CAPT_CONFIG
\end_inset
\end_layout
\begin_layout Description
Type:
Type: read-write
\end_layout
\begin_layout Description
Address: 0x504
......@@ -37131,7 +37137,7 @@ label{LOG_STATUS
\end_inset
\end_layout
\begin_layout Description
Type:
Type: read-only
\end_layout
\begin_layout Description
Address: 0x508
......@@ -37658,7 +37664,7 @@ label{LOG_POINTERS
\end_inset
\end_layout
\begin_layout Description
Type:
Type: read-only
\end_layout
\begin_layout Description
Address: 0x50A
......@@ -38176,7 +38182,7 @@ label{LOG_COMMAND
\end_inset
\end_layout
\begin_layout Description
Type:
Type: write-only
\end_layout
\begin_layout Description
Address: 0x50C
......@@ -38457,7 +38463,7 @@ label{LOG_CAPT_EVENT_1
\end_inset
\end_layout
\begin_layout Description
Type:
Type: read-only
\end_layout
\begin_layout Description
Address: 0x510
......@@ -39458,7 +39464,7 @@ label{LOG_CAPT_EVENT_2
\end_inset
\end_layout
\begin_layout Description
Type:
Type: read-only
\end_layout
\begin_layout Description
Address: 0x514
......
......@@ -33,11 +33,11 @@
/* This file is autogenerated, DO NOT EDIT! */
#ifndef __CTU_CAN_FD_FRAME__
#define __CTU_CAN_FD_FRAME__
#ifndef __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
#define __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
/* Frame_format memory map */
enum ctu_can_fd_frame_format {
/* CAN_Frame_format memory map */
enum ctu_can_fd_can_frame_format {
CTU_CAN_FD_FRAME_FORM_W = 0x0,
CTU_CAN_FD_IDENTIFIER_W = 0x4,
CTU_CAN_FD_TIMESTAMP_L_W = 0x8,
......
......@@ -40,8 +40,7 @@
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Addresses map for: Frame_format
-- Field map for: Frame_format
-- Memory map for: CAN_Frame_format
-- This file is autogenerated, DO NOT EDIT!
--------------------------------------------------------------------------------
......
......@@ -40,8 +40,7 @@
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Addresses map for: Regs
-- Field map for: Regs
-- Memory map for: CAN_Registers
-- This file is autogenerated, DO NOT EDIT!
--------------------------------------------------------------------------------
......@@ -252,12 +251,16 @@ package CAN_FD_register_map is
constant RRB_IND : natural := 10;
constant CDO_IND : natural := 11;
constant ERCRST_IND : natural := 12;
constant RXFCRST_IND : natural := 13;
constant TXFCRST_IND : natural := 14;
-- COMMAND register reset values
constant ABT_RSTVAL : std_logic := '0';
constant RRB_RSTVAL : std_logic := '0';
constant CDO_RSTVAL : std_logic := '0';
constant ERCRST_RSTVAL : std_logic := '0';
constant RXFCRST_RSTVAL : std_logic := '0';
constant TXFCRST_RSTVAL : std_logic := '0';
------------------------------------------------------------------------------
-- STATUS register
......@@ -806,6 +809,7 @@ package CAN_FD_register_map is
------------------------------------------------------------------------------
-- RX_DATA register
--
-- Read data word from RX Buffer.
------------------------------------------------------------------------------
constant RX_DATA_L : natural := 0;
constant RX_DATA_H : natural := 31;
......
......@@ -179,6 +179,63 @@ package CANcomponents is
);
end component;
----------------------------------------------------------------------------
-- Control registers sub-module
----------------------------------------------------------------------------
component control_registers_reg_map is
generic (
constant DATA_WIDTH : natural := 32;
constant ADDRESS_WIDTH : natural := 8;
constant REGISTERED_READ : boolean := true;
constant CLEAR_READ_DATA : boolean := true;
constant RESET_POLARITY : std_logic := "0";
constant SUP_FILT_A : boolean := true;
constant SUP_RANGE : boolean := true;
constant SUP_FILT_C : boolean := true;
constant SUP_FILT_B : boolean := true
);
port (
signal clk_sys :in std_logic;
signal res_n :in std_logic;
signal address :in std_logic_vector(address_width - 1 downto 0);
signal w_data :in std_logic_vector(data_width - 1 downto 0);
signal r_data :out std_logic_vector(data_width - 1 downto 0);
signal cs :in std_logic;
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal control_registers_out :out Control_registers_out_t;
signal control_registers_in :in Control_registers_in_t
);
end component control_registers_reg_map;
----------------------------------------------------------------------------
-- Event logger registers sub-module
----------------------------------------------------------------------------
component event_logger_reg_map is
generic (
constant DATA_WIDTH : natural := 32;
constant ADDRESS_WIDTH : natural := 8;
constant REGISTERED_READ : boolean := true;
constant CLEAR_READ_DATA : boolean := true;
constant RESET_POLARITY : std_logic := "0"
);
port (
signal clk_sys :in std_logic;
signal res_n :in std_logic;
signal address :in std_logic_vector(address_width - 1 downto 0);
signal w_data :in std_logic_vector(data_width - 1 downto 0);
signal r_data :out std_logic_vector(data_width - 1 downto 0);
signal cs :in std_logic;
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal event_logger_out :out Event_Logger_out_t;
signal event_logger_in :in Event_Logger_in_t
);
end component event_logger_reg_map;
----------------------------------------------------------------------------
-- RX Buffer module
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment