Commit 9b930673 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Add more detailed TXT Buffer functional coverage.

parent 47b7a6a6
Pipeline #6134 passed with stage
in 15 seconds
......@@ -263,11 +263,20 @@ begin
begin
-- psl default clock is rising_edge(clk_sys);
-- Each SW command active
-- psl txtb_set_ready_cov : cover (txt_sw_cmd.set_rdy = '1' and sw_cbs = '1');
-- psl txtb_set_empty_cov : cover (txt_sw_cmd.set_ety = '1' and sw_cbs = '1');
-- psl txtb_set_abort_cov : cover (txt_sw_cmd.set_abt = '1' and sw_cbs = '1');
-- psl txtb_set_ready_cov : cover (txt_sw_cmd.set_rdy = '1');
-- psl txtb_set_empty_cov : cover (txt_sw_cmd.set_ety = '1');
-- psl txtb_set_abort_cov : cover (txt_sw_cmd.set_abt = '1');
-- HW Commands
-- psl txtb_hw_lock : cover (txt_hw_cmd.lock = '1' and hw_cbs = '1');
-- psl txtb_hw_unlock : cover (txt_hw_cmd.unlock = '1' and hw_cbs = '1');
-- psl txtb_hw_valid : cover (txt_hw_cmd.valid = '1' and hw_cbs = '1');
-- psl txtb_hw_err : cover (txt_hw_cmd.err = '1' and hw_cbs = '1');
-- psl txtb_hw_arbl : cover (txt_hw_cmd.arbl = '1' and hw_cbs = '1');
-- psl txtb_hw_failed : cover (txt_hw_cmd.failed = '1' and hw_cbs = '1');
end block;
end architecture;
......@@ -357,4 +357,31 @@ begin
end if;
end process;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Functional coverage
----------------------------------------------------------------------------
----------------------------------------------------------------------------
func_cov_block : block
begin
-- psl default clock is rising_edge(clk_sys);
-- Each FSM state
-- psl txtb_fsm_empty : cover (buf_fsm = txt_empty);
-- psl txtb_fsm_ready : cover (buf_fsm = txt_ready);
-- psl txtb_fsm_tx_prog : cover (buf_fsm = txt_tx_prog);
-- psl txtb_fsm_ab_prog : cover (buf_fsm = txt_ab_prog);
-- psl txtb_fsm_error : cover (buf_fsm = txt_error);
-- psl txtb_fsm_aborted : cover (buf_fsm = txt_aborted);
-- psl txtb_fsm_tx_ok : cover (buf_fsm = txt_ok);
-- Simultaneous HW and SW Commands
-- psl txtb_rdy_hazard : cover (txt_hw_cmd.lock = '1' and hw_cbs = '1' and
-- txt_sw_cmd.set_abt = '1' and sw_cbs = '1');
end block;
end architecture;
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