Commit 9b8deb98 authored by Martin Jeřábek's avatar Martin Jeřábek

remove trailing whitespace

parent c0e0859d
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- --
-- CTU CAN FD IP Core -- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 -- Copyright (C) 2015-2018
-- --
-- Authors: -- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com> -- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com> -- Martin Jerabek <martin.jerabek01@gmail.com>
-- --
-- Project advisors: -- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz> -- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz> -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- --
-- Department of Measurement (http://meas.fel.cvut.cz/) -- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz) -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/) -- Czech Technical University (http://www.cvut.cz/)
-- --
-- Permission is hereby granted, free of charge, to any person obtaining a copy -- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"), -- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation -- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense, -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the -- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions: -- Component is furnished to do so, subject to the following conditions:
-- --
-- The above copyright notice and this permission notice shall be included in -- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component. -- all copies or substantial portions of the Component.
-- --
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
...@@ -32,11 +32,11 @@ ...@@ -32,11 +32,11 @@
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT. -- IN THE COMPONENT.
-- --
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch. -- protocol license from Bosch.
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -252,9 +252,9 @@ package CANtestLib is ...@@ -252,9 +252,9 @@ package CANtestLib is
-- SSP (Secondary Sampling Point) configuration options -- SSP (Secondary Sampling Point) configuration options
type SSP_set_command_type is ( type SSP_set_command_type is (
ssp_measured, ssp_measured,
ssp_meas_n_offset, ssp_meas_n_offset,
ssp_offset ssp_offset
); );
-- Use only TRV_DELAY -- Use only TRV_DELAY
-- Use TRV_DELAY + fixed offset given by user -- Use TRV_DELAY + fixed offset given by user
...@@ -467,7 +467,7 @@ package CANtestLib is ...@@ -467,7 +467,7 @@ package CANtestLib is
type SW_CAN_mask_filter_type is ( type SW_CAN_mask_filter_type is (
filter_A, filter_A,
filter_B, filter_B,
filter_C filter_C
); );
...@@ -483,7 +483,7 @@ package CANtestLib is ...@@ -483,7 +483,7 @@ package CANtestLib is
type SW_CAN_range_filter_config is record type SW_CAN_range_filter_config is record
ID_th_low : natural; ID_th_low : natural;
ID_th_high : natural; ID_th_high : natural;
ident_type : std_logic; ident_type : std_logic;
acc_CAN_2_0 : boolean; acc_CAN_2_0 : boolean;
acc_CAN_FD : boolean; acc_CAN_FD : boolean;
end record; end record;
...@@ -516,7 +516,7 @@ package CANtestLib is ...@@ -516,7 +516,7 @@ package CANtestLib is
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Bit sequence generator -- Bit sequence generator
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Longest possible CAN FD Frame is aroud 700 bits. If each bit has opposite -- Longest possible CAN FD Frame is aroud 700 bits. If each bit has opposite
-- polarity than previous one, this could use up to 700 entries. Have some -- polarity than previous one, this could use up to 700 entries. Have some
-- reserve... -- reserve...
...@@ -610,7 +610,7 @@ package CANtestLib is ...@@ -610,7 +610,7 @@ package CANtestLib is
procedure set_error_beh( procedure set_error_beh(
constant error_beh : in err_beh_type constant error_beh : in err_beh_type
); );
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Generates clock signal for the test with custom period, duty cycle and -- Generates clock signal for the test with custom period, duty cycle and
...@@ -921,7 +921,7 @@ package CANtestLib is ...@@ -921,7 +921,7 @@ package CANtestLib is
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Execute write access on Avalon memory bus via Avalon burst. -- Execute write access on Avalon memory bus via Avalon burst.
-- Does not support unaligned accesses. Size of the burst is given by -- Does not support unaligned accesses. Size of the burst is given by
-- length of "w_data". -- length of "w_data".
-- --
...@@ -941,7 +941,7 @@ package CANtestLib is ...@@ -941,7 +941,7 @@ package CANtestLib is
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Execute read access on Avalon memory bus via Avalon burst. -- Execute read access on Avalon memory bus via Avalon burst.
-- Does not support unaligned accesses. Size of the burst is given by -- Does not support unaligned accesses. Size of the burst is given by
-- length of "r_data". -- length of "r_data".
-- --
...@@ -1380,7 +1380,7 @@ package CANtestLib is ...@@ -1380,7 +1380,7 @@ package CANtestLib is
-- --
-- Arguments: -- Arguments:
-- bits Number of Bit times to wait for -- bits Number of Bit times to wait for
-- exit_trans Exit when unit turns transceiver. -- exit_trans Exit when unit turns transceiver.
-- exit_rec Exit when unit turns receiver. -- exit_rec Exit when unit turns receiver.
-- ID Index of CTU CAN FD Core instance -- ID Index of CTU CAN FD Core instance
-- mem_bus Avalon memory bus to execute the access on. -- mem_bus Avalon memory bus to execute the access on.
...@@ -1465,7 +1465,7 @@ package CANtestLib is ...@@ -1465,7 +1465,7 @@ package CANtestLib is
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Set options of RX Buffer. -- Set options of RX Buffer.
-- --
-- Arguments: -- Arguments:
-- options Options to be applied on RX Buffer. -- options Options to be applied on RX Buffer.
...@@ -1798,8 +1798,8 @@ package CANtestLib is ...@@ -1798,8 +1798,8 @@ package CANtestLib is
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Read Timestamp from TIMESTAMP_LOW and TIMESTAMP_HIGH registers -- Read Timestamp from TIMESTAMP_LOW and TIMESTAMP_HIGH registers
-- --
-- Arguments: -- Arguments:
-- ts Variable in which timestamp will be stored -- ts Variable in which timestamp will be stored
-- ID Index of CTU CAN FD Core instance. -- ID Index of CTU CAN FD Core instance.
...@@ -1809,13 +1809,13 @@ package CANtestLib is ...@@ -1809,13 +1809,13 @@ package CANtestLib is
variable ts : out std_logic_vector(63 downto 0); variable ts : out std_logic_vector(63 downto 0);
constant ID : in natural range 0 to 15; constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type signal mem_bus : inout Avalon_mem_type
); );
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Configure SSP (Secondary Sampling Point) configuration: choose applicable -- Configure SSP (Secondary Sampling Point) configuration: choose applicable
-- SSP delaying source and set offest given by the user (if eventually used). -- SSP delaying source and set offest given by the user (if eventually used).
-- --
-- Arguments: -- Arguments:
-- ssp_source Select required source of delaying. -- ssp_source Select required source of delaying.
-- ssp_offset Amount of clock cycles to wait for. -- ssp_offset Amount of clock cycles to wait for.
...@@ -1823,8 +1823,8 @@ package CANtestLib is ...@@ -1823,8 +1823,8 @@ package CANtestLib is
-- mem_bus Avalon memory bus to execute the access on. -- mem_bus Avalon memory bus to execute the access on.
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
procedure CAN_configure_ssp( procedure CAN_configure_ssp(
variable ssp_source : in SSP_set_command_type; variable ssp_source : in SSP_set_command_type;
variable ssp_offset_val : in std_logic_vector(6 downto 0); variable ssp_offset_val : in std_logic_vector(6 downto 0);
constant ID : in natural range 0 to 15; constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type signal mem_bus : inout Avalon_mem_type
); );
...@@ -2039,8 +2039,8 @@ package body CANtestLib is ...@@ -2039,8 +2039,8 @@ package body CANtestLib is
wait for 0 ns; wait for 0 ns;
end procedure; end procedure;
procedure set_log_level( procedure set_log_level(
constant log_level : in log_lvl_type constant log_level : in log_lvl_type
) is ) is
...@@ -2065,8 +2065,8 @@ package body CANtestLib is ...@@ -2065,8 +2065,8 @@ package body CANtestLib is
hide(display_handler, warning); hide(display_handler, warning);
end if; end if;
end procedure; end procedure;
procedure set_error_beh( procedure set_error_beh(
constant error_beh : in err_beh_type constant error_beh : in err_beh_type
) is ) is
...@@ -2076,7 +2076,7 @@ package body CANtestLib is ...@@ -2076,7 +2076,7 @@ package body CANtestLib is
else else
set_stop_level(failure); set_stop_level(failure);
end if; end if;
end procedure; end procedure;
procedure print_test_info( procedure print_test_info(
...@@ -2381,11 +2381,11 @@ package body CANtestLib is ...@@ -2381,11 +2381,11 @@ package body CANtestLib is
constant size : in aval_access_size constant size : in aval_access_size
) return std_logic_vector is ) return std_logic_vector is
begin begin
if (address'length < 2) then if (address'length < 2) then
error("Address to BE conversion. Invalid address"); error("Address to BE conversion. Invalid address");
end if; end if;
if (size = BIT_32) then if (size = BIT_32) then
return "1111"; return "1111";
end if; end if;
...@@ -2423,10 +2423,10 @@ package body CANtestLib is ...@@ -2423,10 +2423,10 @@ package body CANtestLib is
-- Check for access alignment -- Check for access alignment
if (not aval_is_aligned(w_address, w_size)) then if (not aval_is_aligned(w_address, w_size)) then
warning("Unaligned Avalon write, Adress :" & to_hstring(w_address) warning("Unaligned Avalon write, Adress :" & to_hstring(w_address)
& " Size: " & aval_access_size'image(w_size)); & " Size: " & aval_access_size'image(w_size));
else else
w_addr_padded(w_address'length - 1 downto 0) := w_address; w_addr_padded(w_address'length - 1 downto 0) := w_address;
wait until falling_edge(mem_bus.clk_sys); wait until falling_edge(mem_bus.clk_sys);
mem_bus.scs <= '1'; mem_bus.scs <= '1';
mem_bus.swr <= '1'; mem_bus.swr <= '1';
...@@ -2463,8 +2463,8 @@ package body CANtestLib is ...@@ -2463,8 +2463,8 @@ package body CANtestLib is
warning("Unaligned Avalon Read, Adress :" & to_hstring(r_address) & warning("Unaligned Avalon Read, Adress :" & to_hstring(r_address) &
" Size: " & aval_access_size'image(r_size)); " Size: " & aval_access_size'image(r_size));
else else
r_addr_padded(r_address'length - 1 downto 0) := r_address; r_addr_padded(r_address'length - 1 downto 0) := r_address;
wait until falling_edge(mem_bus.clk_sys); wait until falling_edge(mem_bus.clk_sys);
mem_bus.scs <= '1'; mem_bus.scs <= '1';
mem_bus.srd <= '1'; mem_bus.srd <= '1';
...@@ -2524,7 +2524,7 @@ package body CANtestLib is ...@@ -2524,7 +2524,7 @@ package body CANtestLib is
to_hstring(w_address)); to_hstring(w_address));
return; return;
end if; end if;
if (not aval_is_valid_burst_size(w_data'length)) then if (not aval_is_valid_burst_size(w_data'length)) then
return; return;
end if; end if;
...@@ -2538,7 +2538,7 @@ package body CANtestLib is ...@@ -2538,7 +2538,7 @@ package body CANtestLib is
if (not stat_burst) then if (not stat_burst) then
increment := 4; increment := 4;
end if; end if;
act_address(w_address'length - 1 downto 0) := w_address; act_address(w_address'length - 1 downto 0) := w_address;
-- Iterate through the addresses -- Iterate through the addresses
...@@ -2578,7 +2578,7 @@ package body CANtestLib is ...@@ -2578,7 +2578,7 @@ package body CANtestLib is
to_hstring(r_address)); to_hstring(r_address));
return; return;
end if; end if;
if (not aval_is_valid_burst_size(r_data'length)) then if (not aval_is_valid_burst_size(r_data'length)) then
return; return;
end if; end if;
...@@ -2835,7 +2835,7 @@ package body CANtestLib is ...@@ -2835,7 +2835,7 @@ package body CANtestLib is
CAN_write(data, SETTINGS_ADR, ID, mem_bus, BIT_16); CAN_write(data, SETTINGS_ADR, ID, mem_bus, BIT_16);
end procedure; end procedure;
procedure config_filter_frame_types( procedure config_filter_frame_types(
constant ident_type : in std_logic; constant ident_type : in std_logic;
constant acc_CAN_2_0 : in boolean; constant acc_CAN_2_0 : in boolean;
...@@ -3084,7 +3084,7 @@ package body CANtestLib is ...@@ -3084,7 +3084,7 @@ package body CANtestLib is
str_msg(89 to 117) := " RWCNT (read word count): "; str_msg(89 to 117) := " RWCNT (read word count): ";
str_msg(118 to 127) := str_msg(118 to 127) :=
to_string(std_logic_vector(to_unsigned(frame.rwcnt, 10))); to_string(std_logic_vector(to_unsigned(frame.rwcnt, 10)));
-- Data words -- Data words
if (frame.rtr = NO_RTR_FRAME and frame.data_length > 0) then if (frame.rtr = NO_RTR_FRAME and frame.data_length > 0) then
...@@ -3556,7 +3556,7 @@ package body CANtestLib is ...@@ -3556,7 +3556,7 @@ package body CANtestLib is
(bus_timing.prop_dbt + bus_timing.ph1_dbt + (bus_timing.prop_dbt + bus_timing.ph1_dbt +
bus_timing.ph2_dbt + 1); bus_timing.ph2_dbt + 1);
end if; end if;
-- Check Minimal Bit time -- Check Minimal Bit time
check(wait_time > 6, "Calculated Bit Time shorter than minimal!"); check(wait_time > 6, "Calculated Bit Time shorter than minimal!");
...@@ -4450,8 +4450,8 @@ package body CANtestLib is ...@@ -4450,8 +4450,8 @@ package body CANtestLib is
procedure CAN_configure_ssp( procedure CAN_configure_ssp(
variable ssp_source : in SSP_set_command_type; variable ssp_source : in SSP_set_command_type;
variable ssp_offset_val : in std_logic_vector(6 downto 0); variable ssp_offset_val : in std_logic_vector(6 downto 0);
constant ID : in natural range 0 to 15; constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type signal mem_bus : inout Avalon_mem_type
) is ) is
...@@ -4464,7 +4464,7 @@ package body CANtestLib is ...@@ -4464,7 +4464,7 @@ package body CANtestLib is
when ssp_meas_n_offset => when ssp_meas_n_offset =>
data(SSP_SRC_H downto SSP_SRC_L) := SSP_SRC_MEAS_N_OFFSET; --"01"; data(SSP_SRC_H downto SSP_SRC_L) := SSP_SRC_MEAS_N_OFFSET; --"01";
when ssp_offset => when ssp_offset =>
data(SSP_SRC_H downto SSP_SRC_L) := SSP_SRC_OFFSET; --"10"; data(SSP_SRC_H downto SSP_SRC_L) := SSP_SRC_OFFSET; --"10";
when others => when others =>
error("Unsupported SSP type."); error("Unsupported SSP type.");
end case; end case;
...@@ -4488,7 +4488,7 @@ entity CAN_test is ...@@ -4488,7 +4488,7 @@ entity CAN_test is
-- Used only for "reference" test -- Used only for "reference" test
constant data_path :in string := constant data_path :in string :=
"test/reference/data_sets/log_500Kb_2Mb_80p_1K_samples_1" "test/reference/data_sets/log_500Kb_2Mb_80p_1K_samples_1"
); );
port ( port (
......
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