Commit 9abd0ed0 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

TX Buffer command register renamed.

parent a19f4ed0
......@@ -213,11 +213,11 @@ begin
int_input_active(ALI_IND) <= arbitration_lost;
int_input_active(EPI_IND) <= error_passive_changed;
int_input_active(DOI_IND) <= rx_message_disc;
int_input_active(EI_IND) <= error_warning_limit;
int_input_active(TI_IND) <= tx_finished;
int_input_active(RI_IND) <= rec_message_valid;
int_input_active(EWLI_IND) <= error_warning_limit;
int_input_active(TXI_IND) <= tx_finished;
int_input_active(RXI_IND) <= rec_message_valid;
int_input_active(LFI_IND) <= loger_finished;
int_input_active(RFI_IND) <= rx_full;
int_input_active(RXFI_IND) <= rx_full;
int_input_active(BSI_IND) <= br_shifted;
int_input_active(RBNEI_IND) <= not rx_empty;
int_input_active(TXBHCI_IND) <= or_reduce(txt_hw_cmd_int);
......
......@@ -497,7 +497,7 @@ architecture rtl of canfd_registers is
prop_fd <= PROP_FD_RSTVAL;
sam_norm <= TSM_RSTVAL;
ewl <= EWL_LIMIT_RSTVAL;
ewl <= EW_LIMIT_RSTVAL;
erp <= ERP_LIMIT_RSTVAL;
-- Message filters
......@@ -536,10 +536,10 @@ architecture rtl of canfd_registers is
txt_buf_set_ready <= TXCR_RSTVAL;
txt_buf_set_abort <= TXCA_RSTVAL;
txt_buf_cmd_index(0) <= TXI1_RSTVAL;
txt_buf_cmd_index(1) <= TXI2_RSTVAL;
txt_buf_cmd_index(2) <= TXI3_RSTVAL;
txt_buf_cmd_index(3) <= TXI4_RSTVAL;
txt_buf_cmd_index(0) <= TXB1_RSTVAL;
txt_buf_cmd_index(1) <= TXB2_RSTVAL;
txt_buf_cmd_index(2) <= TXB3_RSTVAL;
txt_buf_cmd_index(3) <= TXB4_RSTVAL;
txt_buf_prior(0) <= TXT1P_RSTVAL;
txt_buf_prior(1) <= TXT2P_RSTVAL;
......@@ -1005,8 +1005,8 @@ begin
--------------------------------------------------------
when EWL_ADR =>
-- Error warning limit
write_be_vect(ewl, 0, 7, data_in, EWL_LIMIT_L,
EWL_LIMIT_H, sbe);
write_be_vect(ewl, 0, 7, data_in, EW_LIMIT_L,
EW_LIMIT_H, sbe);
-- Error passive treshold
write_be_vect(erp, 0, 7, data_in, ERP_LIMIT_L,
......@@ -1116,8 +1116,8 @@ begin
-- Vector index for which buffer the command is active
write_be_vect(txt_buf_cmd_index, 0,
TXT_BUFFER_COUNT - 1, data_in, TXI1_IND,
TXI1_IND + txt_buf_cmd_index'length - 1,
TXT_BUFFER_COUNT - 1, data_in, TXB1_IND,
TXB1_IND + txt_buf_cmd_index'length - 1,
sbe);
--------------------------------------------------------
......@@ -1282,7 +1282,7 @@ begin
--------------------------------------------------------
when EWL_ADR =>
-- Error warning limit
data_out_int(EWL_LIMIT_H downto EWL_LIMIT_L) <= ewl;
data_out_int(EW_LIMIT_H downto EW_LIMIT_L) <= ewl;
-- Error passive treshold
data_out_int(ERP_LIMIT_H downto ERP_LIMIT_L) <= erp;
......@@ -1465,10 +1465,10 @@ begin
--------------------------------------------------------
when RX_STATUS_ADR =>
data_out_int <= (OTHERS => '0');
data_out_int(RX_EMPTY_IND) <= rx_empty;
data_out_int(RX_FULL_IND) <= rx_full;
data_out_int(RXE_IND) <= rx_empty;
data_out_int(RXF_IND) <= rx_full;
data_out_int(RX_FRC_H downto RX_FRC_L)
data_out_int(RXFRC_H downto RXFRC_L)
<= rx_message_count;
data_out_int(RTSOP_IND) <= rtsopt;
......
......@@ -3650,7 +3650,7 @@ package body CANtestLib is
end if;
-- Set index of Buffer on which the command should be executed.
data(buf_n + TXI1_IND - 1) := '1';
data(buf_n + TXB1_IND - 1) := '1';
-- Give the command
CAN_write(data, TX_COMMAND_ADR, ID, mem_bus);
......@@ -3713,16 +3713,16 @@ package body CANtestLib is
retVal.rx_full := false;
retVal.rx_empty := false;
if (data(RX_FULL_IND) = '1') then
if (data(RXF_IND) = '1') then
retVal.rx_full := true;
end if;
if (data(RX_EMPTY_IND) = '1') then
if (data(RXE_IND) = '1') then
retVal.rx_empty := true;
end if;
retVal.rx_frame_count := to_integer(unsigned(
data(RX_FRC_H downto RX_FRC_L)));
data(RXFRC_H downto RXFRC_L)));
end procedure;
......@@ -4031,15 +4031,15 @@ package body CANtestLib is
tmp := (OTHERS => '0');
if (interrupts.receive_int) then
tmp(RI_IND) := '1';
tmp(RXI_IND) := '1';
end if;
if (interrupts.transmitt_int) then
tmp(TI_IND) := '1';
tmp(TXI_IND) := '1';
end if;
if (interrupts.error_warning_int) then
tmp(EI_IND) := '1';
tmp(EWLI_IND) := '1';
end if;
if (interrupts.data_overrun_int) then
......@@ -4071,7 +4071,7 @@ package body CANtestLib is
end if;
if (interrupts.rx_buffer_not_empty_int) then
tmp(RBNEI_IND) := '1';
tmp(RBNEWLI_IND) := '1';
end if;
if (interrupts.tx_buffer_hw_cmd) then
......@@ -4090,15 +4090,15 @@ package body CANtestLib is
tmp := (false, false, false, false, false, false,
false, false, false, false, false, false);
if (int_reg(RI_IND) = '1') then
if (int_reg(RXI_IND) = '1') then
tmp.receive_int := true;
end if;
if (int_reg(TI_IND) = '1') then
if (int_reg(TXI_IND) = '1') then
tmp.transmitt_int := true;
end if;
if (int_reg(EI_IND) = '1') then
if (int_reg(EWLI_IND) = '1') then
tmp.error_warning_int := true;
end if;
......@@ -4252,7 +4252,7 @@ package body CANtestLib is
variable data : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
begin
data(EWL_LIMIT_H downto EWL_LIMIT_L) :=
data(EW_LIMIT_H downto EW_LIMIT_L) :=
std_logic_vector(to_unsigned(fault_th.ewl, 8));
data(ERP_LIMIT_H downto ERP_LIMIT_L) :=
......@@ -4273,7 +4273,7 @@ package body CANtestLib is
begin
CAN_read(data, EWL_ADR, ID, mem_bus, BIT_16);
fault_th.ewl := to_integer(unsigned(
data(EWL_LIMIT_H downto EWL_LIMIT_L)));
data(EW_LIMIT_H downto EW_LIMIT_L)));
CAN_read(data, ERP_ADR, ID, mem_bus, BIT_16);
fault_th.erp := to_integer(unsigned(
......
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