Commit 9a8d55f8 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Modified Bit timing registers to have wider ranges for

the bit phases and baud-rate prescaler.
parent 878d188c
This diff is collapsed.
......@@ -47,11 +47,7 @@ enum ctu_can_fd_regs {
CTU_CAN_FD_INT_MASK_SET = 0x14,
CTU_CAN_FD_INT_MASK_CLR = 0x18,
CTU_CAN_FD_BTR = 0x1c,
CTU_CAN_FD_BTR_FD = 0x1e,
CTU_CAN_FD_ALC = 0x20,
CTU_CAN_FD_SJW = 0x21,
CTU_CAN_FD_BRP = 0x22,
CTU_CAN_FD_BRP_FD = 0x23,
CTU_CAN_FD_BTR_FD = 0x20,
CTU_CAN_FD_EWL = 0x24,
CTU_CAN_FD_ERP = 0x25,
CTU_CAN_FD_FAULT_STATE = 0x26,
......@@ -79,6 +75,7 @@ enum ctu_can_fd_regs {
CTU_CAN_FD_TX_COMMAND = 0x6c,
CTU_CAN_FD_TX_PRIORITY = 0x70,
CTU_CAN_FD_ERR_CAPT = 0x74,
CTU_CAN_FD_ALC = 0x75,
CTU_CAN_FD_TRV_DELAY = 0x78,
CTU_CAN_FD_RX_COUNTER = 0x7c,
CTU_CAN_FD_TX_COUNTER = 0x80,
......@@ -340,58 +337,48 @@ union ctu_can_fd_int_mask_clr {
} s;
};
union ctu_can_fd_btr_btr_fd {
union ctu_can_fd_btr {
uint32_t u32;
struct ctu_can_fd_btr_btr_fd_s {
struct ctu_can_fd_btr_s {
#ifdef __BIG_ENDIAN_BITFIELD
/* BTR */
uint32_t prop : 6;
uint32_t ph1 : 5;
uint32_t ph2 : 5;
/* BTR_FD */
uint32_t prop_fd : 6;
uint32_t ph1_fd : 4;
uint32_t reserved_26 : 1;
uint32_t ph2_fd : 4;
uint32_t reserved_31 : 1;
uint32_t prop : 7;
uint32_t ph1 : 6;
uint32_t ph2 : 6;
uint32_t brp : 8;
uint32_t sjw : 5;
#else
uint32_t reserved_31 : 1;
uint32_t ph2_fd : 4;
uint32_t reserved_26 : 1;
uint32_t ph1_fd : 4;
uint32_t prop_fd : 6;
uint32_t ph2 : 5;
uint32_t ph1 : 5;
uint32_t prop : 6;
uint32_t sjw : 5;
uint32_t brp : 8;
uint32_t ph2 : 6;
uint32_t ph1 : 6;
uint32_t prop : 7;
#endif
} s;
};
union ctu_can_fd_alc_sjw_brp_brp_fd {
union ctu_can_fd_btr_fd {
uint32_t u32;
struct ctu_can_fd_alc_sjw_brp_brp_fd_s {
struct ctu_can_fd_btr_fd_s {
#ifdef __BIG_ENDIAN_BITFIELD
/* ALC */
uint32_t alc_val : 5;
uint32_t reserved_7_5 : 3;
/* SJW */
uint32_t sjw : 4;
uint32_t sjw_fd : 4;
/* BRP */
uint32_t brp : 6;
uint32_t reserved_23_22 : 2;
/* BRP_FD */
uint32_t brp_fd : 6;
uint32_t reserved_31_30 : 2;
/* BTR_FD */
uint32_t prop_fd : 6;
uint32_t reserved_6 : 1;
uint32_t ph1_fd : 5;
uint32_t reserved_12 : 1;
uint32_t ph2_fd : 5;
uint32_t reserved_18 : 1;
uint32_t brp_fd : 8;
uint32_t sjw_fd : 5;
#else
uint32_t reserved_31_30 : 2;
uint32_t brp_fd : 6;
uint32_t reserved_23_22 : 2;
uint32_t brp : 6;
uint32_t sjw_fd : 4;
uint32_t sjw : 4;
uint32_t reserved_7_5 : 3;
uint32_t alc_val : 5;
uint32_t sjw_fd : 5;
uint32_t brp_fd : 8;
uint32_t reserved_18 : 1;
uint32_t ph2_fd : 5;
uint32_t reserved_12 : 1;
uint32_t ph1_fd : 5;
uint32_t reserved_6 : 1;
uint32_t prop_fd : 6;
#endif
} s;
};
......@@ -795,16 +782,19 @@ union ctu_can_fd_tx_priority {
} s;
};
union ctu_can_fd_err_capt {
union ctu_can_fd_err_capt_alc {
uint32_t u32;
struct ctu_can_fd_err_capt_s {
struct ctu_can_fd_err_capt_alc_s {
#ifdef __BIG_ENDIAN_BITFIELD
/* ERR_CAPT */
uint32_t err_pos : 5;
uint32_t err_type : 3;
uint32_t reserved_31_8 : 24;
/* ALC */
uint32_t alc_val : 5;
uint32_t reserved_31_13 : 19;
#else
uint32_t reserved_31_8 : 24;
uint32_t reserved_31_13 : 19;
uint32_t alc_val : 5;
uint32_t err_type : 3;
uint32_t err_pos : 5;
#endif
......
......@@ -812,28 +812,28 @@
<ipxact:register>
<ipxact:name>BTR_FD</ipxact:name>
<ipxact:displayName>BTR_FD</ipxact:displayName>
<ipxact:description>Length of bit time segments for Data bit time in Time quanta. Note that SYNC segment always lasts one Time quanta.</ipxact:description>
<ipxact:description>Bit timing register for data bit-rate.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h1E</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
<ipxact:addressOffset>'h20</ipxact:addressOffset>
<ipxact:size>32</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-write</ipxact:access>
<ipxact:field>
<ipxact:name>PH2_FD</ipxact:name>
<ipxact:displayName>PH2_FD</ipxact:displayName>
<ipxact:description>Phase 2 segment - Data bit time</ipxact:description>
<ipxact:bitOffset>11</ipxact:bitOffset>
<ipxact:description>Phase 2 segment</ipxact:description>
<ipxact:bitOffset>13</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>3</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>4</ipxact:bitWidth>
<ipxact:bitWidth>5</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>PROP_FD</ipxact:name>
<ipxact:displayName>PROP_FD</ipxact:displayName>
<ipxact:description>Propagation segment - Data bit time</ipxact:description>
<ipxact:description>Propagation segment</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -845,14 +845,36 @@
<ipxact:field>
<ipxact:name>PH1_FD</ipxact:name>
<ipxact:displayName>PH1_FD</ipxact:displayName>
<ipxact:description>Phase 1 segment - Data bit time</ipxact:description>
<ipxact:bitOffset>6</ipxact:bitOffset>
<ipxact:description>Phase 1 segment</ipxact:description>
<ipxact:bitOffset>7</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>3</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>4</ipxact:bitWidth>
<ipxact:bitWidth>5</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>BRP_FD</ipxact:name>
<ipxact:description>Baud-rate prescaler</ipxact:description>
<ipxact:bitOffset>19</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>4</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>SJW_FD</ipxact:name>
<ipxact:description>Synchronisation jump width</ipxact:description>
<ipxact:bitOffset>27</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>2</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>5</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
......@@ -882,147 +904,91 @@
<ipxact:register>
<ipxact:name>BTR</ipxact:name>
<ipxact:displayName>BTR</ipxact:displayName>
<ipxact:description>The length of bit time segments for Nominal bit time in Time quanta. Note that SYNC segment always lasts one Time quanta.</ipxact:description>
<ipxact:description>Bit timing register for nominal bit-rate.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h1C</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
<ipxact:size>32</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-write</ipxact:access>
<ipxact:field>
<ipxact:name>PROP</ipxact:name>
<ipxact:displayName>PROP</ipxact:displayName>
<ipxact:description>Propagation segment - Nominal bit time</ipxact:description>
<ipxact:description>Propagation segment</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>5</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>6</ipxact:bitWidth>
<ipxact:bitWidth>7</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>PH1</ipxact:name>
<ipxact:displayName>PH1</ipxact:displayName>
<ipxact:description>Phase 1 segment - Nominal bit time</ipxact:description>
<ipxact:bitOffset>6</ipxact:bitOffset>
<ipxact:description>Phase 1 segment</ipxact:description>
<ipxact:bitOffset>7</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>3</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>5</ipxact:bitWidth>
<ipxact:bitWidth>6</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>PH2</ipxact:name>
<ipxact:displayName>PH2</ipxact:displayName>
<ipxact:description>Phase 2 segment - Nominal bit time</ipxact:description>
<ipxact:bitOffset>11</ipxact:bitOffset>
<ipxact:description>Phase 2 segment</ipxact:description>
<ipxact:bitOffset>13</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>5</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>5</ipxact:bitWidth>
<ipxact:bitWidth>6</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
<ipxact:name>ALC</ipxact:name>
<ipxact:displayName>ALC</ipxact:displayName>
<ipxact:description>Arbitration lost capture register. </ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h20</ipxact:addressOffset>
<ipxact:size>8</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-only</ipxact:access>
<ipxact:field>
<ipxact:name>ALC_VAL</ipxact:name>
<ipxact:displayName>ALC_VAL</ipxact:displayName>
<ipxact:description>Arbitration lost capture value. Not supported yet. Do not use!</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:name>BRP</ipxact:name>
<ipxact:description>Baud-rate prescaler</ipxact:description>
<ipxact:bitOffset>19</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
<ipxact:value>'hA</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>5</ipxact:bitWidth>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
<ipxact:name>SJW</ipxact:name>
<ipxact:displayName>SJW</ipxact:displayName>
<ipxact:description>Synchronisation jump width registers for both Nominal and Data bit times.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h21</ipxact:addressOffset>
<ipxact:size>8</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-write</ipxact:access>
<ipxact:field>
<ipxact:name>SJW</ipxact:name>
<ipxact:displayName>SJW</ipxact:displayName>
<ipxact:description>Synchronisation jump width - Nominal bit time.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>2</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>4</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>SJW_FD</ipxact:name>
<ipxact:displayName>SJW_FD</ipxact:displayName>
<ipxact:description>Synchronisation jump widh - Data bit time.</ipxact:description>
<ipxact:bitOffset>4</ipxact:bitOffset>
<ipxact:description>Synchronisation jump width</ipxact:description>
<ipxact:bitOffset>27</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>2</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>4</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
<ipxact:name>BRP</ipxact:name>
<ipxact:displayName>BRP</ipxact:displayName>
<ipxact:description>Baud rate Prescaler register - Nominal bit time. </ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h22</ipxact:addressOffset>
<ipxact:size>8</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-write</ipxact:access>
<ipxact:field>
<ipxact:name>BRP</ipxact:name>
<ipxact:displayName>BRP</ipxact:displayName>
<ipxact:description>Specifies time quanta duration for nominal bit time.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>10</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>6</ipxact:bitWidth>
<ipxact:bitWidth>5</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
<ipxact:name>BRP_FD</ipxact:name>
<ipxact:displayName>BRP_FD</ipxact:displayName>
<ipxact:description>Baud rate Prescaler register - Data bit time. </ipxact:description>
<ipxact:name>ALC</ipxact:name>
<ipxact:displayName>ALC</ipxact:displayName>
<ipxact:description>Arbitration lost capture register. </ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h23</ipxact:addressOffset>
<ipxact:addressOffset>'h75</ipxact:addressOffset>
<ipxact:size>8</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-write</ipxact:access>
<ipxact:access>read-only</ipxact:access>
<ipxact:field>
<ipxact:name>BRP_FD</ipxact:name>
<ipxact:displayName>BRP_FD</ipxact:displayName>
<ipxact:description>Specifies time quanta duration for data bit time.</ipxact:description>
<ipxact:name>ALC_VAL</ipxact:name>
<ipxact:displayName>ALC_VAL</ipxact:displayName>
<ipxact:description>Arbitration lost capture value. Not supported yet. Do not use!</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>4</ipxact:value>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>6</ipxact:bitWidth>
<ipxact:bitWidth>5</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
......@@ -1501,7 +1467,7 @@
<ipxact:description>Last error frame capture.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h74</ipxact:addressOffset>
<ipxact:size>32</ipxact:size>
<ipxact:size>8</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-only</ipxact:access>
<ipxact:field>
......
......@@ -61,8 +61,8 @@
-- use hard-coded value of time quanta during ph1 and ph2 bit times.
--------------------------------------------------------------------------------
-- Revision History:
-- July 2015 Created file
--
-- Oct 2017 Created file
-- 13.3.2018 Modified bit phases lengths
--------------------------------------------------------------------------------
Library ieee;
......@@ -72,12 +72,12 @@ USE WORK.CANconstants.ALL;
package brs_comp_package is
procedure brs_comp(
signal tq_nbt : in natural range 0 to 63;
signal tq_dbt : in natural range 0 to 63;
signal tq_nbt : in natural range 0 to 255;
signal tq_dbt : in natural range 0 to 255;
signal sp_control : in std_logic_vector(1 downto 0);
signal ph2_nbt : in natural range 0 to 63;
signal ph2_dbt : in natural range 0 to 15;
signal ph2_real : out integer range -63 to 63
signal ph2_dbt : in natural range 0 to 31;
signal ph2_real : out integer range -127 to 127
);
end brs_comp_package;
......@@ -92,12 +92,12 @@ package body brs_comp_package is
-- sp_control update, actual update of the ph2_real), compensation
-- of the ph2_real is needed based on Time quanta(TQ) duration
procedure brs_comp(
signal tq_nbt : in natural range 0 to 63;
signal tq_dbt : in natural range 0 to 63;
signal tq_nbt : in natural range 0 to 255;
signal tq_dbt : in natural range 0 to 255;
signal sp_control : in std_logic_vector(1 downto 0);
signal ph2_nbt : in natural range 0 to 63;
signal ph2_dbt : in natural range 0 to 15;
signal ph2_real : out integer range -63 to 63
signal ph2_dbt : in natural range 0 to 31;
signal ph2_real : out integer range -127 to 127
)is
variable ntd : boolean; --Nominal to Data switch
begin
......
......@@ -103,6 +103,8 @@
-- "drv_" prefix.
-- 12.12.2017 Added "brs_comp" compensation for the compensation of phase2
-- During the bit where bit rate switch occured.
-- 13.03.2018 Modified bit phases length to have more options in SW settings
-- of bit-timings.
--------------------------------------------------------------------------------
Library ieee;
......@@ -189,13 +191,13 @@ entity prescaler_v3 is
--Number of mminimal time quantum (sys clock) in time quantum , Nominal
--BitTimeNumber of mminimal time quantum (sys clock) in time quantum ,
--Nominal BitTime
signal drv_tq_nbt : std_logic_vector (5 downto 0);
signal drv_tq_nbt : std_logic_vector (7 downto 0);
--Number of mminimal time quantum (sys clock) in time quantum , Data BitTime
signal drv_tq_dbt : std_logic_vector (5 downto 0);
signal drv_tq_dbt : std_logic_vector (7 downto 0);
--Propagation segment length in nominal bit time
signal drv_prs_nbt : std_logic_vector (5 downto 0);
signal drv_prs_nbt : std_logic_vector (6 downto 0);
--Phase 1 segment length nominal bit time
signal drv_ph1_nbt : std_logic_vector (5 downto 0);
......@@ -204,34 +206,34 @@ entity prescaler_v3 is
signal drv_ph2_nbt : std_logic_vector (5 downto 0);
--Propagation segment length in nominal bit time
signal drv_prs_dbt : std_logic_vector (3 downto 0);
signal drv_prs_dbt : std_logic_vector (5 downto 0);
--Phase 1 segment length nominal bit time
signal drv_ph1_dbt : std_logic_vector (3 downto 0);
signal drv_ph1_dbt : std_logic_vector (4 downto 0);
--Phase 2 segment length nominal bit time
signal drv_ph2_dbt : std_logic_vector (3 downto 0);
signal drv_ph2_dbt : std_logic_vector (4 downto 0);
--Synchronisation jump width
signal drv_sjw_nbt : std_logic_vector(3 downto 0);
signal drv_sjw_nbt : std_logic_vector(4 downto 0);
--Synchronisation jump width
signal drv_sjw_dbt : std_logic_vector(3 downto 0);
signal drv_sjw_dbt : std_logic_vector(4 downto 0);
------------------------------------------------------------------------------
--Driving bus aliases converted to integer (signed, natural)
-- Integer aliases used for simplification of the code !!
------------------------------------------------------------------------------
signal tq_nbt : natural range 0 to 63;
signal tq_dbt : natural range 0 to 63;
signal prs_nbt : natural range 0 to 63;
signal prs_dbt : natural range 0 to 15;
signal ph1_nbt : natural range 0 to 63;
signal ph1_dbt : natural range 0 to 15;
signal ph2_nbt : natural range 0 to 63;
signal ph2_dbt : natural range 0 to 15;
signal sjw_nbt : natural range 0 to 15;
signal sjw_dbt : natural range 0 to 15;
signal tq_nbt : natural range 0 to 255;
signal tq_dbt : natural range 0 to 255;
signal prs_nbt : natural range 0 to 127;
signal prs_dbt : natural range 0 to 63;
signal ph1_nbt : natural range 0 to 63;
signal ph1_dbt : natural range 0 to 31;
signal ph2_nbt : natural range 0 to 63;
signal ph2_dbt : natural range 0 to 31;
signal sjw_nbt : natural range 0 to 31;
signal sjw_dbt : natural range 0 to 31;
----------------------
--INTERNAL REGISTERS--
......@@ -249,7 +251,7 @@ entity prescaler_v3 is
signal tq_edge : std_logic;
--Bit time counter
signal bt_counter : natural range 0 to 63;
signal bt_counter : natural range 0 to 255;
--Hard synchronisation appeared
signal hard_sync_valid : std_logic;
......@@ -279,7 +281,7 @@ entity prescaler_v3 is
---------------------
--Time quantum duration
signal tq_dur : natural range 0 to 63;
signal tq_dur : natural range 0 to 255;
------------------
--Bit time type --
......@@ -288,10 +290,10 @@ entity prescaler_v3 is
signal is_tran_trig : boolean;
--Duration of ph1 segment after synchronisation
signal ph1_real : integer range -63 to 63;
signal ph1_real : integer range -127 to 127;
--Duration of ph2 segment after synchronisation
signal ph2_real : integer range -63 to 63;
signal ph2_real : integer range -127 to 127;
end entity;
......@@ -396,8 +398,8 @@ begin
end process;
--New time quantum period detection
tq_edge <= '1' when (sp_control=NOMINAL_SAMPLE) and (drv_tq_nbt="000001") else
'1' when (sp_control=DATA_SAMPLE) and (drv_tq_dbt="000001") else
tq_edge <= '1' when (sp_control=NOMINAL_SAMPLE) and (drv_tq_nbt="00000001") else
'1' when (sp_control=DATA_SAMPLE) and (drv_tq_dbt="00000001") else
'1' when (tq_counter=1) else
'0';
......
......@@ -65,11 +65,7 @@ package CAN_FD_register_map is
constant INT_MASK_SET_ADR : std_logic_vector(11 downto 0) := x"014";
constant INT_MASK_CLR_ADR : std_logic_vector(11 downto 0) := x"018";
constant BTR_ADR : std_logic_vector(11 downto 0) := x"01C";
constant BTR_FD_ADR : std_logic_vector(11 downto 0) := x"01E";
constant ALC_ADR : std_logic_vector(11 downto 0) := x"020";
constant SJW_ADR : std_logic_vector(11 downto 0) := x"021";
constant BRP_ADR : std_logic_vector(11 downto 0) := x"022";
constant BRP_FD_ADR : std_logic_vector(11 downto 0) := x"023";
constant BTR_FD_ADR : std_logic_vector(11 downto 0) := x"020";
constant EWL_ADR : std_logic_vector(11 downto 0) := x"024";
constant ERP_ADR : std_logic_vector(11 downto 0) := x"025";
constant FAULT_STATE_ADR : std_logic_vector(11 downto 0) := x"026";
......@@ -97,6 +93,7 @@ package CAN_FD_register_map is
constant TX_COMMAND_ADR : std_logic_vector(11 downto 0) := x"06C";
constant TX_PRIORITY_ADR : std_logic_vector(11 downto 0) := x"070";
constant ERR_CAPT_ADR : std_logic_vector(11 downto 0) := x"074";
constant ALC_ADR : std_logic_vector(11 downto 0) := x"075";
constant TRV_DELAY_ADR : std_logic_vector(11 downto 0) := x"078";
constant RX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"07C";
constant TX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"080";
......@@ -407,85 +404,48 @@ package CAN_FD_register_map is
------------------------------------------------------------------------------
-- BTR register
--
-- The length of bit time segments for Nominal bit time in Time quanta. Note t
-- hat SYNC segment always lasts one Time quanta.
-- Bit timing register for nominal bit-rate.
------------------------------------------------------------------------------
constant PROP_L : natural := 0;
constant PROP_H : natural := 5;
constant PH1_L : natural := 6;
constant PH1_H : natural := 10;
constant PH2_L : natural := 11;
constant PH2_H : natural := 15;
constant PROP_H : natural := 6;
constant PH1_L : natural := 7;