Commit 99be551d authored by Martin Jeřábek's avatar Martin Jeřábek

feature tests: stage 1

parent 005dd4bf
This diff is collapsed.
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.math_real.ALL;
use work.CANconstants.all;
USE work.CANtestLib.All;
USE work.randomLib.All;
package pkg_feature_exec_dispath is
--Procedure for processing the feature tests!
procedure exec_feature_test(
--Common test parameters
signal test_name : in string;
variable outcome : inout boolean;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
--Additional signals for tests
--Pretty much everything can be read out of stat bus...
signal mem_bus_1 : inout Avalon_mem_type;
signal mem_bus_2 : inout Avalon_mem_type;
signal int_1 : in std_logic;
signal int_2 : in std_logic;
signal bus_level : in std_logic;
signal drv_bus_1 : in std_logic_vector(1023 downto 0);
signal drv_bus_2 : in std_logic_vector(1023 downto 0);
signal stat_bus_1 : in std_logic_vector(511 downto 0);
signal stat_bus_2 : in std_logic_vector(511 downto 0);
signal bl_inject : inout std_logic;
signal bl_force : inout boolean
);
end package;
This diff is collapsed.
...@@ -3573,61 +3573,6 @@ entity CAN_test is ...@@ -3573,61 +3573,6 @@ entity CAN_test is
end entity; end entity;
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.math_real.ALL;
USE work.randomLib.All;
use work.CANconstants.all;
USE work.CANtestLib.All;
--------------------------------------------------------------------------------
-- Test enity for feature tests. Additional signals representing two memory
-- buses are present to connect two DUTs of feature tests!
--------------------------------------------------------------------------------
entity CAN_feature_test is
port (
-- Input trigger, test starts running when true
signal run : in boolean;
-- Number of iterations that test should do
signal iterations : in natural;
-- Logging level, severity which should be shown
signal log_level : in log_lvl_type;
-- Test behaviour when error occurs: Quit, or Go on
signal error_beh : in err_beh_type;
-- Error tolerance, error counter should not
-- exceed this value in order for the test to pass
signal error_tol : in natural;
-- Status of the test
signal status : out test_status_type;
-- Amount of errors which appeared in the test
signal errors : out natural;
-- Memory access buses
signal mem_bus_1 : inout Avalon_mem_type;
signal mem_bus_2 : inout Avalon_mem_type;
-- Bus level injected value and whether it should be forced on bus
signal bl_inject : in std_logic;
signal bl_force : in boolean
);
-- Internal test signals
signal error_ctr : natural := 0;
signal loop_ctr : natural := 0;
signal exit_imm : boolean := false;
signal rand_ctr : natural range 0 to 3800 := 0;
end entity;
USE work.CANtestLib.All; USE work.CANtestLib.All;
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
......
...@@ -99,7 +99,7 @@ def test(obj, config, vunit_args): ...@@ -99,7 +99,7 @@ def test(obj, config, vunit_args):
# check for unknown tests # check for unknown tests
all_benches = lib.get_test_benches('*') all_benches = lib.get_test_benches('*')
unknown_tests = [tb for tb in all_benches if not re.match('tb_.*?_unit_test|tb_sanity', tb.name)] unknown_tests = [tb for tb in all_benches if not re.match('tb_.*?_unit_test|tb_sanity|tb_feature', tb.name)]
if len(unknown_tests): if len(unknown_tests):
log.warn('Unknown tests (defaults will be used): {}'.format(', '.join(tb.name for tb in unknown_tests))) log.warn('Unknown tests (defaults will be used): {}'.format(', '.join(tb.name for tb in unknown_tests)))
......
Library ieee;
library vunit_lib;
library work;
context vunit_lib.vunit_context;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.math_real.ALL;
use work.CANconstants.all;
USE work.CANtestLib.All;
USE work.randomLib.All;
--Testbench packages
{% for test in tests %}
use work.{{ test }}_feature.All;
{% endfor %}
package body pkg_feature_exec_dispath is
--Procedure for processing the feature tests!
procedure exec_feature_test(
--Common test parameters
signal test_name : in string;
variable outcome : inout boolean;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
--Additional signals for tests
--Pretty much everything can be read out of stat bus...
signal mem_bus_1 : inout Avalon_mem_type;
signal mem_bus_2 : inout Avalon_mem_type;
signal int_1 : in std_logic;
signal int_2 : in std_logic;
signal bus_level : in std_logic;
signal drv_bus_1 : in std_logic_vector(1023 downto 0);
signal drv_bus_2 : in std_logic_vector(1023 downto 0);
signal stat_bus_1 : in std_logic_vector(511 downto 0);
signal stat_bus_2 : in std_logic_vector(511 downto 0);
signal bl_inject : inout std_logic;
signal bl_force : inout boolean
) is
begin
outcome:=false;
-- TODO: generate this procedure
if false then
{% for test in tests %}
elsif run("{{ test }}") then
{{ test }}_feature_exec(outcome,rand_ctr,mem_bus_1,mem_bus_2,bus_level,
drv_bus_1,drv_bus_2,stat_bus_1,stat_bus_2);
{% endfor %}
end if;
end procedure;
end package body;
import logging import logging
from pathlib import Path
from .test_common import * from .test_common import *
log = logging.getLogger(__name__) log = logging.getLogger(__name__)
class FeatureTests(TestsBase): class FeatureTests(TestsBase):
def add_sources(self): def __init__(self, *args, **kwds):
add_sources(self.lib, ['feature/**/*.vhd']) super().__init__(*args, **kwds)
self._tests = self.config['tests'].keys()
def configure(self): def add_sources(self) -> None:
sources = ['feature/{}_feature_tb.vhd'.format(name) for name in self._tests]
sources.append('feature/tb_feature.vhd')
sources.append('feature/pkg_feature_exec_dispatch.vhd')
add_sources(self.lib, sources)
wrname = self.build / 'pkg_feature_exec_dispatch-body.vhd';
self._create_wrapper(wrname)
#add_sources(self.lib, [str(wrname)])
self.lib.add_source_file(str(wrname))
tb = self.lib.get_test_benches('*tb_feature')[0]
tb.scan_tests_from_file(str(wrname))
def configure(self) -> None:
# TODO: iterations ...
pass pass
def _create_wrapper(self, ofile : Path) -> None:
template = self.jinja_env.get_template('pkg_feature_exec_dispath-body.vhd')
c = template.render(tests=self._tests)
with ofile.open('wt', encoding='utf-8') as f:
f.write(c)
unit: .unit:
default: default:
log_level: warning log_level: warning
error_tolerance: 0 error_tolerance: 0
...@@ -31,7 +31,25 @@ unit: ...@@ -31,7 +31,25 @@ unit:
wave: unit/TX_Arbitrator/txar_unit.tcl wave: unit/TX_Arbitrator/txar_unit.tcl
tx_buf: tx_buf:
wave: unit/TX_Buffer/txbf_unit.tcl wave: unit/TX_Buffer/txbf_unit.tcl
sanity: feature:
default:
tests:
abort_transmittion:
#arbitration:
fault_confinement:
forbid_fd:
#interrupt:
invalid_configs:
overload:
retr_limit:
#rx_status:
#soft_reset:
spec_mode:
traf_meas:
tran_delay:
tx_arb_time_tran:
.sanity:
default: default:
iterations: 1 iterations: 1
timeout: 2 sec timeout: 2 sec
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment