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CTU CAN FD IP Core
Commit 98779f0c authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
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Merge branch '68-separate-rx-buffer-write-pointers' into 'master' 

Resolve "Separate RX Buffer write pointers"

Closes #68

See merge request illeondr/CAN_FD_IP_Core!68
parents 013fe415 18040b3b
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Showing with 2198 additions and 1781 deletions
modelsim_project/CAN_FD_IP_Core.mpf
View file @ 98779f0c
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src/Buffers_Message_Handling/rxBuffer.vhd
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src/CAN_Core/core_top.vhd
View file @ 98779f0c
......@@ -151,15 +151,20 @@ entity core_top is
--Error state indicator
signal rec_esi_out :out std_logic;
--Output from acceptance filters (out_ident_valid) if message fits the filters
-- Acknowledge that CAN frame was received succesfully and can be
-- committed in the RX Buffer
signal rec_message_valid_out :out std_logic;
--Acknowledge for CAN Core about accepted data
signal rec_message_ack_out :in std_logic;
signal rec_dram_word_out :out std_logic_vector(31 downto 0);
signal rec_dram_addr_out :in natural range 0 to 15;
-- Metadata are received OK, and can be stored in RX Buffer!
signal store_metadata :out std_logic;
-- Data words is available and can be stored in RX Buffer!
signal store_data :out std_logic;
signal store_data_word :out std_logic_vector(31 downto 0);
-- Cancel storing of frame in RX Buffer.
signal rec_abort :out std_logic;
-------------------------------
--Interrupt Manager Interface--
-------------------------------
......@@ -440,8 +445,6 @@ entity core_top is
signal rec_esi : std_logic;
signal ack_recieved_out : std_logic;
signal rec_dram_word : std_logic_vector(31 downto 0);
signal rec_dram_addr : natural range 0 to 15;
--CRC Interfaces
--Transition from 0 to 1 erases the CRC and operation holds as long
......@@ -527,12 +530,9 @@ begin
rec_is_rtr_out <= rec_is_rtr;
rec_brs_out <= rec_brs;
rec_esi_out <= rec_esi;
rec_dram_word_out <= rec_dram_word;
rec_dram_addr <= rec_dram_addr_out;
--Confirmation about valid recieved data for RX Buffer
rec_message_valid_out <= rec_valid;
--rec_message_ack_out
--NOTE: HandShake protocol with acknowledge not used in the end
-- Transceive CAN frame is routed directly
......@@ -598,8 +598,11 @@ begin
rec_brs => rec_brs,
rec_crc => rec_crc,
rec_esi => rec_esi,
rec_dram_word => rec_dram_word,
rec_dram_addr => rec_dram_addr,
store_metadata => store_metadata,
rec_abort => rec_abort,
store_data => store_data,
store_data_word => store_data_word,
OP_state => OP_state,
arbitration_lost => arbitration_lost,
......
src/CAN_Core/protocolControl.vhd
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src/CAN_top_level.vhd
View file @ 98779f0c
......@@ -294,9 +294,6 @@ entity CAN_top_level is
--Message Identifier
signal rec_ident_in : std_logic_vector(28 downto 0);
--Message Data (up to 64 bytes);
signal rec_data_in : std_logic_vector(511 downto 0);
--Data length code
signal rec_dlc_in : std_logic_vector(3 downto 0);
......@@ -309,24 +306,29 @@ entity CAN_top_level is
--Recieved frame is RTR Frame(0-No, 1-Yes)
signal rec_is_rtr : std_logic;
--Frame is received properly
--Frame is received properly (can be committed to RX Buffer)
signal rec_message_valid : std_logic;
--Whenever frame was recieved with BIT Rate shift
signal rec_brs : std_logic;
--Acknowledge for CAN Core about accepted data
signal rec_message_ack : std_logic;
-- Received Error state indicator
signal rec_esi : std_logic;
-- Signals start of frame for storing timestamp
signal sof_pulse : std_logic;
-- Pointer to RX Ram in CAN Core and output word with the received data
signal rec_dram_word : std_logic_vector(31 downto 0);
signal rec_dram_addr : natural range 0 to 15;
-- Metadata can be stored to the RX Buffer
signal rx_store_metadata : std_logic;
-- Data word can be stored in RX Buffer
signal rx_store_data : std_logic;
-- Data word to be stored
signal rx_store_data_word : std_logic_vector(31 downto 0);
-- Abort storing of RX Frame (in case of Error frame)
signal rx_abort : std_logic;
------------------------------------------------------------------------------
......@@ -504,7 +506,6 @@ begin
rx_mem_free => rx_mem_free,
rx_read_pointer_pos => rx_read_pointer_pos,
rx_write_pointer_pos => rx_write_pointer_pos,
rx_message_disc => rx_message_disc,
rx_data_overrun => rx_data_overrun,
tran_data => tran_data,
tran_addr => tran_addr,
......@@ -524,41 +525,43 @@ begin
log_state_out => log_state_out
);
rx_buf_comp : rxBuffer
rx_buf_comp : rxBuffer
generic map(
buff_size => rx_buffer_size
)
buff_size => rx_buffer_size
)
port map(
clk_sys => clk_sys,
res_n => res_n_int,
rec_ident_in => rec_ident_in,
rec_dlc_in => rec_dlc_in,
rec_ident_type_in => rec_ident_type_in,
rec_frame_type_in => rec_frame_type_in,
rec_is_rtr => rec_is_rtr,
--Note: This has to be confirmed from Message filters not CAN Core
rec_message_valid => out_ident_valid,
rec_brs => rec_brs,
rec_esi => rec_esi,
rec_message_ack => rec_message_ack,
rec_dram_word => rec_dram_word,
rec_dram_addr => rec_dram_addr,
rx_buf_size => rx_buf_size,
rx_full => rx_full,
rx_empty => rx_empty,
rx_message_count => rx_message_count,
rx_mem_free => rx_mem_free,
rx_read_pointer_pos => rx_read_pointer_pos,
rx_write_pointer_pos => rx_write_pointer_pos,
rx_message_disc => rx_message_disc,
rx_data_overrun => rx_data_overrun,
rx_read_buff => rx_read_buff,
sof_pulse => sof_pulse,
timestamp => timestamp,
drv_bus => drv_bus
);
clk_sys => clk_sys,
res_n => res_n_int,
rec_ident_in => rec_ident_in,
rec_dlc_in => rec_dlc_in,
rec_ident_type_in => rec_ident_type_in,
rec_frame_type_in => rec_frame_type_in,
rec_is_rtr => rec_is_rtr,
rec_brs => rec_brs,
rec_esi => rec_esi,
store_metadata => out_ident_valid,
store_data => rx_store_data,
store_data_word => rx_store_data_word,
rec_message_valid => rec_message_valid,
rec_abort => rx_abort,
sof_pulse => sof_pulse,
rx_buf_size => rx_buf_size,
rx_full => rx_full,
rx_empty => rx_empty,
rx_message_count => rx_message_count,
rx_mem_free => rx_mem_free,
rx_read_pointer_pos => rx_read_pointer_pos,
rx_write_pointer_pos => rx_write_pointer_pos,
rx_data_overrun => rx_data_overrun,
timestamp => timestamp,
rx_read_buff => rx_read_buff,
drv_bus => drv_bus
);
txt_buf_comp_gen : for i in 0 to TXT_BUFFER_COUNT - 1 generate
......@@ -625,7 +628,9 @@ begin
rec_ident_in => rec_ident_in,
ident_type => rec_ident_type_in,
frame_type => rec_frame_type_in,
rec_ident_valid => rec_message_valid,
-- Identifier comparison can be done when metadata are received!
rec_ident_valid => rx_store_metadata,
drv_bus => drv_bus,
out_ident_valid => out_ident_valid
);
......@@ -643,7 +648,7 @@ begin
arbitration_lost => arbitration_lost,
tx_finished => tx_finished,
br_shifted => br_shifted,
rx_message_disc => rx_message_disc,
rx_message_disc => rx_data_overrun,
rec_message_valid => rec_message_valid,
rx_full => rx_full,
rx_empty => rx_empty,
......@@ -680,9 +685,12 @@ begin
rec_brs_out => rec_brs,
rec_esi_out => rec_esi,
rec_message_valid_out => rec_message_valid,
rec_message_ack_out => rec_message_ack,
rec_dram_word_out => rec_dram_word,
rec_dram_addr_out => rec_dram_addr,
store_metadata => rx_store_metadata,
rec_abort => rx_abort,
store_data => rx_store_data,
store_data_word => rx_store_data_word,
arbitration_lost_out => arbitration_lost,
tx_finished => tx_finished,
br_shifted => br_shifted,
......
src/Libraries/CANcomponents.vhd
View file @ 98779f0c
......@@ -139,7 +139,6 @@ package CANcomponents is
signal rx_mem_free : in std_logic_vector(12 downto 0);
signal rx_read_pointer_pos : in std_logic_vector(11 downto 0);
signal rx_write_pointer_pos : in std_logic_vector(11 downto 0);
signal rx_message_disc : in std_logic;
signal rx_data_overrun : in std_logic;
signal tran_data : out std_logic_vector(31 downto 0);
signal tran_addr : out std_logic_vector(4 downto 0);
......@@ -164,38 +163,39 @@ package CANcomponents is
-- RX Buffer module
------------------------------------------------------------------------------
component rxBuffer is
GENERIC(
buff_size : natural range 32 to 4096 := 32
);
PORT(
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async. reset
signal rec_ident_in :in std_logic_vector(28 downto 0);
signal rec_dlc_in :in std_logic_vector(3 downto 0);
signal rec_ident_type_in :in std_logic;
signal rec_frame_type_in :in std_logic;
signal rec_is_rtr :in std_logic;
signal rec_brs :in std_logic;
signal rec_esi :in std_logic;
signal rec_message_ack :out std_logic;
signal rec_message_valid :in std_logic;
signal rec_dram_word :in std_logic_vector(31 downto 0);
signal rec_dram_addr :out natural range 0 to 15;
signal rx_buf_size :out std_logic_vector(12 downto 0);
signal rx_full :out std_logic;
signal rx_empty :out std_logic;
signal rx_message_count :out std_logic_vector(10 downto 0);
signal rx_mem_free :out std_logic_vector(12 downto 0);
signal rx_read_pointer_pos :out std_logic_vector(11 downto 0);
signal rx_write_pointer_pos :out std_logic_vector(11 downto 0);
signal rx_message_disc :out std_logic;
signal rx_data_overrun :out std_logic;
signal timestamp :in std_logic_vector(63 downto 0);
signal rx_read_buff :out std_logic_vector(31 downto 0);
signal sof_pulse :in std_logic;
signal drv_bus :in std_logic_vector(1023 downto 0)
);
end component;
generic(
buff_size : natural range 32 to 4096 := 32
);
port(
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async. reset
signal rec_ident_in :in std_logic_vector(28 downto 0);
signal rec_dlc_in :in std_logic_vector(3 downto 0);
signal rec_ident_type_in :in std_logic;
signal rec_frame_type_in :in std_logic;
signal rec_is_rtr :in std_logic;
signal rec_brs :in std_logic;
signal rec_esi :in std_logic;
signal store_metadata :in std_logic;
signal store_data :in std_logic;
signal store_data_word :in std_logic_vector(31 downto 0);
signal rec_message_valid :in std_logic;
signal rec_abort :in std_logic;
signal sof_pulse :in std_logic;
signal rx_buf_size :out std_logic_vector(12 downto 0);
signal rx_full :out std_logic;
signal rx_empty :out std_logic;
signal rx_message_count :out std_logic_vector(10 downto 0);
signal rx_mem_free :out std_logic_vector(12 downto 0);
signal rx_read_pointer_pos :out std_logic_vector(11 downto 0);
signal rx_write_pointer_pos :out std_logic_vector(11 downto 0);
signal rx_data_overrun :out std_logic;
signal timestamp :in std_logic_vector(63 downto 0);
signal rx_read_buff :out std_logic_vector(31 downto 0);
signal drv_bus :in std_logic_vector(1023 downto 0)
);
end component;
------------------------------------------------------------------------------
--TX Buffer module
......@@ -367,6 +367,7 @@ package CANcomponents is
signal txt_hw_cmd : out txt_hw_cmd_type;
signal txtb_changed : in std_logic;
signal txt_buf_ptr : out natural range 0 to 19;
signal rec_ident_out : out std_logic_vector(28 downto 0);
signal rec_dlc_out : out std_logic_vector(3 downto 0);
signal rec_ident_type_out : out std_logic;
......@@ -375,9 +376,11 @@ package CANcomponents is
signal rec_brs_out : out std_logic;
signal rec_esi_out : out std_logic;
signal rec_message_valid_out : out std_logic;
signal rec_message_ack_out : in std_logic;
signal rec_dram_word_out : out std_logic_vector(31 downto 0);
signal rec_dram_addr_out : in natural range 0 to 15;
signal store_metadata : out std_logic;
signal store_data : out std_logic;
signal store_data_word : out std_logic_vector(31 downto 0);
signal rec_abort : out std_logic;
signal arbitration_lost_out : out std_logic;
signal tx_finished : out std_logic;
signal br_shifted : out std_logic;
......@@ -635,8 +638,10 @@ package CANcomponents is
signal rec_brs : out std_logic;
signal rec_crc : out std_logic_vector(20 downto 0);
signal rec_esi : out std_logic;
signal rec_dram_word : out std_logic_vector(31 downto 0);
signal rec_dram_addr : in natural range 0 to 15;
signal store_metadata : out std_logic;
signal rec_abort : out std_logic;
signal store_data : out std_logic;
signal store_data_word : out std_logic_vector(31 downto 0);
signal OP_state : in oper_mode_type;
signal arbitration_lost : out std_logic;
signal is_idle : out std_logic;
......
src/Libraries/CANconstants.vhd
View file @ 98779f0c
......@@ -246,6 +246,18 @@ package CANconstants is
running
);
-- RX Buffer loader type
type rx_buf_fsm_type is (
rxb_idle,
rxb_store_frame_format,
rxb_store_identifier,
rxb_store_beg_ts_low,
rxb_store_beg_ts_high,
rxb_store_end_ts_low,
rxb_store_end_ts_high,
rxb_store_data
);
-- TX arbitrator state type
type tx_arb_state_type is (
arb_sel_low_ts,
......
src/Registers_Memory_Interface/canfd_registers.vhd
View file @ 98779f0c
......@@ -194,11 +194,8 @@ entity canfd_registers is
--Position of write pointer
signal rx_write_pointer_pos :in std_logic_vector(11 downto 0);
--Frame was discarded due full Memory
signal rx_message_disc :in std_logic;
--Some data were discarded, register
--Some data were discarded, register
signal rx_data_overrun :in std_logic;
--------------------------------------------------------
......
test/lib/CANtestLib.vhd
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test/lib/randomLib.vhd
View file @ 98779f0c
......@@ -73,63 +73,63 @@ USE ieee.math_real.ALL;
package randomLib is
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Probability distributions
--
-- Distribution parameters are different for every distribution. Each of
-- the following subsections contains one
----------------------------------------------------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Probability distributions
--
-- Distribution parameters are different for every distribution. Each of
-- the following subsections contains one
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Types of probability distributions
type rand_distribution_type is(
-- Types of probability distributions
type rand_distribution_type is(
GAUSS,
EXPONENTIAL
);
-- Distribution parameters
constant DISTR_PAR_COUNT : natural := 5;
type rand_distribution_par_type is
array (0 to DISTR_PAR_COUNT - 1) of real;
-- Distribution parameters
constant DISTR_PAR_COUNT : natural := 5;
type rand_distribution_par_type is
array (0 to DISTR_PAR_COUNT - 1) of real;
----------------------------------------------------------------------------
-- GAUSS (Normal) distribution
--
-- GAUS_mean Mean value of Normal distribution
-- GAUS_vairance Variance of Normal distribution
-- GAUS_iterations Number of summations in central limit
-- theorem, to calculate the result.
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- GAUSS (Normal) distribution
--
-- GAUS_mean Mean value of Normal distribution
-- GAUS_vairance Variance of Normal distribution
-- GAUS_iterations Number of summations in central limit
-- theorem, to calculate the result.
----------------------------------------------------------------------------
constant GAUSS_mean : natural := 0;
constant GAUSS_variance : natural := 1;
constant GAUSS_iterations : natural := 2;
----------------------------------------------------------------------------
-- Exponential distribution
--
-- EXPONENTIAL_mean Mean value of Exponential distribution
----------------------------------------------------------------------------
-- Exponential distribution
--
-- EXPONENTIAL_mean Mean value of Exponential distribution
-- (or so called, "scale" parameter)
----------------------------------------------------------------------------
constant EXPONENTIAL_mean : natural := 0;
----------------------------------------------------------------------------
constant EXPONENTIAL_mean : natural := 0;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Uniformly distributed random pool stuff
----------------------------------------------------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Uniformly distributed random pool stuff
----------------------------------------------------------------------------
----------------------------------------------------------------------------
constant RAND_POOL_SIZE : natural := 3800;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Function declarations
----------------------------------------------------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Function declarations
----------------------------------------------------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Get random value of type "real" from random pool. Signal output.
......@@ -307,17 +307,35 @@ package randomLib is
);
----------------------------------------------------------------------------
-- Waits for random number of clock cycles with minimum and maximum amount
-- of cycles to wait.
--
-- Arguments:
-- real_ctr Pointer to random data pool
-- clk Clock on which wait should be executed!
-- min Minimum amount of cycles to wait
-- max Maximum amount of cycles to wait
----------------------------------------------------------------------------
procedure wait_rand_cycles(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal clk : in std_logic;
constant min : in integer;
constant max : in integer
);
----------------------------------------------------------------------------
-- Get random value of type real. Repetitive calls of this function return
-- random numbers with selected distribution.
-- random numbers with selected distribution.
--
-- Arguments:
-- real_ctr Pointer to random data pool
-- retval Variable in which returned value will be stored
-- distribution Probability distribution of successive returned values.
-- parameters Parameters of probability distribution. Reffer to
-- description of "rand_distribution_type" for further
-- explanation.
-- distribution Probability distribution of successive returned values.
-- parameters Parameters of probability distribution. Reffer to
-- description of "rand_distribution_type" for further
-- explanation.
--
----------------------------------------------------------------------------
procedure rand_real_distr_v(
......@@ -1323,6 +1341,28 @@ package body randomLib is
end procedure;
procedure wait_rand_cycles(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal clk : in std_logic;
constant min : in integer;
constant max : in integer
)is
variable rand_val : natural;
begin
if (max < min) then
report "Invalid input parameters, MAX lower than MIN" severity
error;
else
rand_int_v(real_ctr, max - min, rand_val);
rand_val := rand_val + min;
for i in 0 to rand_val loop
wait until rising_edge(clk);
end loop;
end if;
end procedure;
procedure rand_logic_vect_bt_v(
signal real_ctr : inout natural range 0 to RAND_POOL_SIZE;
variable retVal : inout std_logic_vector;
......
test/sanity/sanity_test.vhd
View file @ 98779f0c
......@@ -453,6 +453,7 @@ architecture behavioral of sanity_test is
variable RX_frame : SW_CAN_frame_type;
variable comp_out : boolean;
variable detected : boolean := false;
variable node_error : boolean := false;
begin
outcome := true;
tx_r_ptr := 0;
......@@ -463,7 +464,9 @@ architecture behavioral of sanity_test is
-- own frames)!
for i in 1 to NODE_COUNT loop
node_error := false;
tx_r_ptr := 0;
for j in 1 to NODE_COUNT loop
if (i /= j) then
......@@ -494,10 +497,32 @@ architecture behavioral of sanity_test is
if (detected = false) then
outcome:= false;
node_error := true;
end if;
end loop;
end if;
end loop;
-- Print contents of test memories for each node if something
-- went wrong!
if (node_error) then
tx_r_ptr := 0;
log("TX Memory Node " & integer'image(i) & ":",
error_l, log_level);
while (tx_mems(i)(tx_r_ptr)(8) = '1') loop
read_frame_from_mem(TX_frame, tx_mems, i, tx_r_ptr);
CAN_print_frame(TX_frame, error_l);
end loop;
log("RX Memory Node " & integer'image(i) & ":",
error_l, log_level);
rx_r_ptr := 0;
while (rx_mems(i)(rx_r_ptr)(8) = '1') loop
read_frame_from_mem(RX_frame, rx_mems, i, rx_r_ptr);
CAN_print_frame(RX_frame, error_l);
end loop;
end if;
end loop;
end procedure;
......
test/unit/RX_Buffer/RX_Buffer_model.vhd deleted 100644 → 0
View file @ 013fe415
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisors and co-authors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- Martin Jerabek <jerabma7@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------