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Commit 98779f0c authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
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Merge branch '68-separate-rx-buffer-write-pointers' into 'master' 

Resolve "Separate RX Buffer write pointers"

Closes #68

See merge request illeondr/CAN_FD_IP_Core!68
parents 013fe415 18040b3b
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Showing with 2198 additions and 1781 deletions
modelsim_project/CAN_FD_IP_Core.mpf
View file @ 98779f0c
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src/Buffers_Message_Handling/rxBuffer.vhd
View file @ 98779f0c
This diff is collapsed.
src/CAN_Core/core_top.vhd
View file @ 98779f0c
......@@ -151,15 +151,20 @@ entity core_top is
--Error state indicator
signal rec_esi_out :out std_logic;
--Output from acceptance filters (out_ident_valid) if message fits the filters
-- Acknowledge that CAN frame was received succesfully and can be
-- committed in the RX Buffer
signal rec_message_valid_out :out std_logic;
--Acknowledge for CAN Core about accepted data
signal rec_message_ack_out :in std_logic;
signal rec_dram_word_out :out std_logic_vector(31 downto 0);
signal rec_dram_addr_out :in natural range 0 to 15;
-- Metadata are received OK, and can be stored in RX Buffer!
signal store_metadata :out std_logic;
-- Data words is available and can be stored in RX Buffer!
signal store_data :out std_logic;
signal store_data_word :out std_logic_vector(31 downto 0);
-- Cancel storing of frame in RX Buffer.
signal rec_abort :out std_logic;
-------------------------------
--Interrupt Manager Interface--
-------------------------------
......@@ -440,8 +445,6 @@ entity core_top is
signal rec_esi : std_logic;
signal ack_recieved_out : std_logic;
signal rec_dram_word : std_logic_vector(31 downto 0);
signal rec_dram_addr : natural range 0 to 15;
--CRC Interfaces
--Transition from 0 to 1 erases the CRC and operation holds as long
......@@ -527,12 +530,9 @@ begin
rec_is_rtr_out <= rec_is_rtr;
rec_brs_out <= rec_brs;
rec_esi_out <= rec_esi;
rec_dram_word_out <= rec_dram_word;
rec_dram_addr <= rec_dram_addr_out;
--Confirmation about valid recieved data for RX Buffer
rec_message_valid_out <= rec_valid;
--rec_message_ack_out
--NOTE: HandShake protocol with acknowledge not used in the end
-- Transceive CAN frame is routed directly
......@@ -598,8 +598,11 @@ begin
rec_brs => rec_brs,
rec_crc => rec_crc,
rec_esi => rec_esi,
rec_dram_word => rec_dram_word,
rec_dram_addr => rec_dram_addr,
store_metadata => store_metadata,
rec_abort => rec_abort,
store_data => store_data,
store_data_word => store_data_word,
OP_state => OP_state,
arbitration_lost => arbitration_lost,
......
src/CAN_Core/protocolControl.vhd
View file @ 98779f0c
......@@ -196,6 +196,9 @@
-- 6.4.2018 Added direct addressing of identifier from Protocol control.
-- In SOF TXT buffer pointer is set to identifier word and
-- Identifier is stored in the first cycle of Arbitration field.
-- 19.5.2018 Added "store_data", "store_metadata", "rec_abort" signals
-- as a storing protocol between CAN Core and RX Buffer for
-- continous storing of CAN frame during reception.
--------------------------------------------------------------------------------
Library ieee;
......@@ -236,10 +239,10 @@ entity protocolControl is
--Pointer to TXT buffer memory
signal txt_buf_ptr :out natural range 0 to 19;
signal txtb_changed :in std_logic;
signal txtb_changed :in std_logic;
-------------------------
--Recieved data output --
-- RX Buffer interface
-------------------------
signal rec_ident :out std_logic_vector(28 downto 0);
signal rec_dlc :out std_logic_vector(3 downto 0);
......@@ -250,10 +253,16 @@ entity protocolControl is
signal rec_crc :out std_logic_vector(20 downto 0);
signal rec_esi :out std_logic;
--Added interface for aux SRAM
signal rec_dram_word :out std_logic_vector(31 downto 0);
signal rec_dram_addr :in natural range 0 to 15;
-- Metadata are received OK, and can be stored in RX Buffer!
signal store_metadata :out std_logic;
-- Cancel storing of frame in RX Buffer.
signal rec_abort :out std_logic;
-- Data words is available and can be stored in RX Buffer!
signal store_data :out std_logic;
signal store_data_word :out std_logic_vector(31 downto 0);
--------------------------------
--Operation mode FSM Interface--
--------------------------------
......@@ -526,6 +535,16 @@ entity protocolControl is
--Recieved Error state indicator
signal rec_esi_r : std_logic;
-- Metadata are received OK, and can be stored in RX Buffer!
signal store_metadata_r : std_logic;
-- Cancel storing of frame in RX Buffer.
signal rec_abort_r : std_logic;
-- Data words is available and can be stored in RX Buffer!
signal store_data_r : std_logic;
signal store_data_word_r : std_logic_vector(31 downto 0);
-------------------------
--Arbitration registers--
......@@ -585,20 +604,17 @@ entity protocolControl is
--Pointer for transcieving the stuf length field
signal stl_pointer : natural range 0 to 3;
signal data_size : natural range 0 to 511;
-- Signals for optimalization of data reception usage
-- Refer to Revision comment: 29.11.2017
type rec_data_RAM_type is array (0 to 15) of std_logic_vector(31 downto 0);
--Shift register for data reception
signal rec_data_sr : std_logic_vector(7 downto 0);
--Register for counting received bytes in shift register
signal rec_dram_ptr : natural range 0 to 7;
signal rec_word_ptr : natural range 0 to 7;
--Byte index into RAM
signal rec_dram_bind : natural range 0 to 3;
signal rec_dram : rec_data_RAM_type;
--Byte index into RAM word (store_data_word)
signal rec_word_bind : natural range 0 to 3;
--Pointer directly to TXT buffer to get the data
signal txt_buf_ptr_r : natural range 0 to 19;
......@@ -738,8 +754,15 @@ begin
rec_brs <= rec_brs_r;
rec_crc <= rec_crc_r;
rec_esi <= rec_esi_r;
store_metadata <= store_metadata_r;
rec_abort <= rec_abort_r;
store_data <= store_data_r;
store_data_word <= store_data_word_r;
ack_recieved_out <= ack_recieved;
--Pointer into TXT Buffer
txt_buf_ptr <= txt_buf_ptr_r;
......@@ -769,12 +792,7 @@ begin
--Parity of the stuff length field
-------------------------------------
stuff_parity <= '0' when (dst_ctr mod 2)=0 else
'1';
-------------------------------------
-- Output of receive data RAM
-------------------------------------
rec_dram_word <= rec_dram(rec_dram_addr);
'1';
---------------------------------------
---------------------------------------
......@@ -862,17 +880,23 @@ begin
tran_ident_base_sr <= (OTHERS => '0');
tran_ident_ext_sr <= (OTHERS => '0');
--Nulling recieve registers
-- Nulling recieve registers
rec_ident_base_sr <= (OTHERS=>'0');
rec_ident_ext_sr <= (OTHERS=>'0');
rec_dlc_r <= (OTHERS=>'0');
rec_is_rtr_r <= '0';
rec_ident_type_r <= '0';
rec_frame_type_r <= '0';
-- Commands for RX Buffer for storing received frame
store_metadata_r <= '0';
rec_abort_r <= '0';
store_data_r <= '0';
store_data_word_r <= (OTHERS=>'0');
-- Receive data RAM
rec_dram_ptr <= 0;
rec_dram_bind <= 0;
rec_word_ptr <= 0;
rec_word_bind <= 0;
rec_data_sr <= (OTHERS => '0');
-- Pointer directly to TXT Buffer RAM
......@@ -931,6 +955,7 @@ begin
fixed_destuff_r <= fixed_destuff_r;
destuff_length_r <= destuff_length_r;
stuff_error_enable_r <= stuff_error_enable_r;
rec_ident_base_sr <= rec_ident_base_sr;
rec_ident_ext_sr <= rec_ident_ext_sr;
rec_dlc_r <= rec_dlc_r;
......@@ -940,6 +965,12 @@ begin
rec_brs_r <= rec_brs_r;
rec_crc_r <= rec_crc_r;
rec_esi_r <= rec_esi_r;
store_metadata_r <= '0';
rec_abort_r <= '0';
store_data_r <= '0';
store_data_word_r <= store_data_word_r;
tran_pointer <= tran_pointer;
arb_state <= arb_state;--Arbitration control state machine
arb_two_bits <= arb_two_bits;
......@@ -1030,12 +1061,12 @@ begin
rx_count_grey <= rx_count_grey;
rec_data_sr <= rec_data_sr;
rec_dram_ptr <= rec_dram_ptr;
rec_dram_bind <= rec_dram_bind;
rec_word_ptr <= rec_word_ptr;
rec_word_bind <= rec_word_bind;
txt_buf_ptr_r <= txt_buf_ptr_r;
sof_pulse_r <= sof_pulse_r;
sof_pulse_r <= '0';
if(drv_ena='0')then
PC_State <= off;
......@@ -1675,7 +1706,7 @@ begin
rec_dlc_r(0) <= data_rx;
FSM_preset <= '1';
--If frame is RTR Frame or dat length is zero
--If frame is RTR Frame or data length is zero
if((rec_is_rtr_r=RTR_FRAME and rec_frame_type_r=NORMAL_CAN) or
(rec_dlc_r(3 downto 1)="000" and data_rx='0'))then
PC_State <= crc;
......@@ -1695,6 +1726,10 @@ begin
dlc_int(3 downto 1) <= rec_dlc_r(3 downto 1);
dlc_int(0) <= data_rx;
end if;
-- Sending commands to RX Buffer, to store metadata,
-- identifier and frame format words
store_metadata_r <= '1';
when others=>
unknown_state_Error_r <= '1';
......@@ -1747,8 +1782,8 @@ begin
end if;
--Receive RAM signals
rec_dram_ptr <= 0;
rec_dram_bind <= 0;
rec_word_ptr <= 0;
rec_word_bind <= 0;
rec_data_sr <= (OTHERS => '0');
-- Pointer directly to TXT Buffer, First data word
......@@ -1765,7 +1800,9 @@ begin
--Move to the next word
if ((data_pointer mod 32) = 0) then
txt_buf_ptr_r <= txt_buf_ptr_r + 1;
if (txt_buf_ptr_r < 19) then
txt_buf_ptr_r <= txt_buf_ptr_r + 1;
end if;
end if;
end if;
......@@ -1776,42 +1813,56 @@ begin
--Recieving data (also transmitter recieves the same data)
if(rec_trig='1')then
-- Shift register and storing to local RAM
rec_data_sr <= rec_data_sr(6 downto 0)&data_rx;
rec_dram_ptr <= (rec_dram_ptr+1) mod 8;
-- Shift register and bits within one byte
rec_data_sr <= rec_data_sr(6 downto 0) & data_rx;
rec_word_ptr <= (rec_word_ptr + 1) mod 8;
-- If the whole byte was received
if (rec_dram_ptr=7) then
rec_dram_bind <= (rec_dram_bind+1) mod 4;
case rec_dram_bind is
-- If whole byte was received store it to "store_data_word_r".
if (rec_word_ptr = 7) then
rec_word_bind <= (rec_word_bind + 1) mod 4;
case rec_word_bind is
when 0 =>
rec_dram(data_pointer/32) <= rec_data_sr(6 downto 0) &
store_data_word_r <= rec_data_sr(6 downto 0) &
data_rx &
"000000000000000000000000";
when 1 =>
rec_dram(data_pointer/32)(23 downto 0) <=
store_data_word_r(23 downto 0) <=
rec_data_sr(6 downto 0) &
data_rx &
"0000000000000000";
when 2 =>
rec_dram(data_pointer/32)(15 downto 0) <=
store_data_word_r(15 downto 0) <=
rec_data_sr(6 downto 0) &
data_rx &
"00000000";
when 3 =>
rec_dram(data_pointer/32)(7 downto 0) <=
store_data_word_r(7 downto 0) <=
rec_data_sr(6 downto 0)&
data_rx;
when others =>
report "Unknown state" severity error;
PC_State <= error;
end case;
end case;
-- Give command to RX Buffer to store data word if 4 byte
-- aligned data were received!
if (rec_word_bind = 3 and OP_State = reciever) then
store_data_r <= '1';
end if;
end if;
if(data_pointer>511-data_size)then
--if(data_pointer>0)then
data_pointer <= data_pointer-1;
else
-- If we finish data field, and we did not receive 4 byte aligned
-- data, we still did not store data since last aligned word!
-- Remaining bytes must be stored
if (rec_word_bind /= 3 and OP_State = reciever) then
store_data_r <= '1';
end if;
PC_State <= crc;
FSM_Preset <= '1';
end if;
......@@ -2359,6 +2410,9 @@ begin
--This helps in situations when error is detected during Data bit
--rates!!
data_tx_r <= DOMINANT;
-- Storing in RX Buffer must be aborted regardless of OP State.
rec_abort_r <= '1';
--If unit is transciever and Error appears then rettransmitt
-- counter should be incremented
......
src/CAN_top_level.vhd
View file @ 98779f0c
......@@ -294,9 +294,6 @@ entity CAN_top_level is
--Message Identifier
signal rec_ident_in : std_logic_vector(28 downto 0);
--Message Data (up to 64 bytes);
signal rec_data_in : std_logic_vector(511 downto 0);
--Data length code
signal rec_dlc_in : std_logic_vector(3 downto 0);
......@@ -309,24 +306,29 @@ entity CAN_top_level is
--Recieved frame is RTR Frame(0-No, 1-Yes)
signal rec_is_rtr : std_logic;
--Frame is received properly
--Frame is received properly (can be committed to RX Buffer)
signal rec_message_valid : std_logic;
--Whenever frame was recieved with BIT Rate shift
signal rec_brs : std_logic;
--Acknowledge for CAN Core about accepted data
signal rec_message_ack : std_logic;
-- Received Error state indicator
signal rec_esi : std_logic;
-- Signals start of frame for storing timestamp
signal sof_pulse : std_logic;
-- Pointer to RX Ram in CAN Core and output word with the received data
signal rec_dram_word : std_logic_vector(31 downto 0);
signal rec_dram_addr : natural range 0 to 15;
-- Metadata can be stored to the RX Buffer
signal rx_store_metadata : std_logic;
-- Data word can be stored in RX Buffer
signal rx_store_data : std_logic;
-- Data word to be stored
signal rx_store_data_word : std_logic_vector(31 downto 0);
-- Abort storing of RX Frame (in case of Error frame)
signal rx_abort : std_logic;
------------------------------------------------------------------------------
......@@ -504,7 +506,6 @@ begin
rx_mem_free => rx_mem_free,
rx_read_pointer_pos => rx_read_pointer_pos,
rx_write_pointer_pos => rx_write_pointer_pos,
rx_message_disc => rx_message_disc,
rx_data_overrun => rx_data_overrun,
tran_data => tran_data,
tran_addr => tran_addr,
......@@ -524,41 +525,43 @@ begin
log_state_out => log_state_out
);
rx_buf_comp : rxBuffer
rx_buf_comp : rxBuffer
generic map(
buff_size => rx_buffer_size
)
buff_size => rx_buffer_size
)
port map(
clk_sys => clk_sys,
res_n => res_n_int,
rec_ident_in => rec_ident_in,
rec_dlc_in => rec_dlc_in,
rec_ident_type_in => rec_ident_type_in,
rec_frame_type_in => rec_frame_type_in,
rec_is_rtr => rec_is_rtr,
--Note: This has to be confirmed from Message filters not CAN Core
rec_message_valid => out_ident_valid,
rec_brs => rec_brs,
rec_esi => rec_esi,
rec_message_ack => rec_message_ack,
rec_dram_word => rec_dram_word,
rec_dram_addr => rec_dram_addr,
rx_buf_size => rx_buf_size,
rx_full => rx_full,
rx_empty => rx_empty,
rx_message_count => rx_message_count,
rx_mem_free => rx_mem_free,
rx_read_pointer_pos => rx_read_pointer_pos,
rx_write_pointer_pos => rx_write_pointer_pos,
rx_message_disc => rx_message_disc,
rx_data_overrun => rx_data_overrun,
rx_read_buff => rx_read_buff,
sof_pulse => sof_pulse,
timestamp => timestamp,
drv_bus => drv_bus
);
clk_sys => clk_sys,
res_n => res_n_int,
rec_ident_in => rec_ident_in,
rec_dlc_in => rec_dlc_in,
rec_ident_type_in => rec_ident_type_in,
rec_frame_type_in => rec_frame_type_in,
rec_is_rtr => rec_is_rtr,
rec_brs => rec_brs,
rec_esi => rec_esi,
store_metadata => out_ident_valid,
store_data => rx_store_data,
store_data_word => rx_store_data_word,
rec_message_valid => rec_message_valid,
rec_abort => rx_abort,
sof_pulse => sof_pulse,
rx_buf_size => rx_buf_size,
rx_full => rx_full,
rx_empty => rx_empty,
rx_message_count => rx_message_count,
rx_mem_free => rx_mem_free,
rx_read_pointer_pos => rx_read_pointer_pos,
rx_write_pointer_pos => rx_write_pointer_pos,
rx_data_overrun => rx_data_overrun,
timestamp => timestamp,
rx_read_buff => rx_read_buff,
drv_bus => drv_bus
);
txt_buf_comp_gen : for i in 0 to TXT_BUFFER_COUNT - 1 generate
......@@ -625,7 +628,9 @@ begin
rec_ident_in => rec_ident_in,
ident_type => rec_ident_type_in,
frame_type => rec_frame_type_in,
rec_ident_valid => rec_message_valid,
-- Identifier comparison can be done when metadata are received!
rec_ident_valid => rx_store_metadata,
drv_bus => drv_bus,
out_ident_valid => out_ident_valid
);
......@@ -643,7 +648,7 @@ begin
arbitration_lost => arbitration_lost,
tx_finished => tx_finished,
br_shifted => br_shifted,
rx_message_disc => rx_message_disc,
rx_message_disc => rx_data_overrun,
rec_message_valid => rec_message_valid,
rx_full => rx_full,
rx_empty => rx_empty,
......@@ -680,9 +685,12 @@ begin
rec_brs_out => rec_brs,
rec_esi_out => rec_esi,
rec_message_valid_out => rec_message_valid,
rec_message_ack_out => rec_message_ack,
rec_dram_word_out => rec_dram_word,
rec_dram_addr_out => rec_dram_addr,
store_metadata => rx_store_metadata,
rec_abort => rx_abort,
store_data => rx_store_data,
store_data_word => rx_store_data_word,
arbitration_lost_out => arbitration_lost,
tx_finished => tx_finished,
br_shifted => br_shifted,
......
src/Libraries/CANcomponents.vhd
View file @ 98779f0c
......@@ -139,7 +139,6 @@ package CANcomponents is
signal rx_mem_free : in std_logic_vector(12 downto 0);
signal rx_read_pointer_pos : in std_logic_vector(11 downto 0);
signal rx_write_pointer_pos : in std_logic_vector(11 downto 0);
signal rx_message_disc : in std_logic;
signal rx_data_overrun : in std_logic;
signal tran_data : out std_logic_vector(31 downto 0);
signal tran_addr : out std_logic_vector(4 downto 0);
......@@ -164,38 +163,39 @@ package CANcomponents is
-- RX Buffer module
------------------------------------------------------------------------------
component rxBuffer is
GENERIC(
buff_size : natural range 32 to 4096 := 32
);
PORT(
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async. reset
signal rec_ident_in :in std_logic_vector(28 downto 0);
signal rec_dlc_in :in std_logic_vector(3 downto 0);
signal rec_ident_type_in :in std_logic;
signal rec_frame_type_in :in std_logic;
signal rec_is_rtr :in std_logic;
signal rec_brs :in std_logic;
signal rec_esi :in std_logic;
signal rec_message_ack :out std_logic;
signal rec_message_valid :in std_logic;
signal rec_dram_word :in std_logic_vector(31 downto 0);
signal rec_dram_addr :out natural range 0 to 15;
signal rx_buf_size :out std_logic_vector(12 downto 0);
signal rx_full :out std_logic;
signal rx_empty :out std_logic;
signal rx_message_count :out std_logic_vector(10 downto 0);
signal rx_mem_free :out std_logic_vector(12 downto 0);
signal rx_read_pointer_pos :out std_logic_vector(11 downto 0);
signal rx_write_pointer_pos :out std_logic_vector(11 downto 0);
signal rx_message_disc :out std_logic;
signal rx_data_overrun :out std_logic;
signal timestamp :in std_logic_vector(63 downto 0);
signal rx_read_buff :out std_logic_vector(31 downto 0);
signal sof_pulse :in std_logic;
signal drv_bus :in std_logic_vector(1023 downto 0)
);
end component;
generic(
buff_size : natural range 32 to 4096 := 32
);
port(
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async. reset
signal rec_ident_in :in std_logic_vector(28 downto 0);
signal rec_dlc_in :in std_logic_vector(3 downto 0);
signal rec_ident_type_in :in std_logic;
signal rec_frame_type_in :in std_logic;
signal rec_is_rtr :in std_logic;
signal rec_brs :in std_logic;
signal rec_esi :in std_logic;
signal store_metadata :in std_logic;
signal store_data :in std_logic;
signal store_data_word :in std_logic_vector(31 downto 0);
signal rec_message_valid :in std_logic;
signal rec_abort :in std_logic;
signal sof_pulse :in std_logic;
signal rx_buf_size :out std_logic_vector(12 downto 0);
signal rx_full :out std_logic;
signal rx_empty :out std_logic;
signal rx_message_count :out std_logic_vector(10 downto 0);
signal rx_mem_free :out std_logic_vector(12 downto 0);
signal rx_read_pointer_pos :out std_logic_vector(11 downto 0);
signal rx_write_pointer_pos :out std_logic_vector(11 downto 0);
signal rx_data_overrun :out std_logic;
signal timestamp :in std_logic_vector(63 downto 0);
signal rx_read_buff :out std_logic_vector(31 downto 0);
signal drv_bus :in std_logic_vector(1023 downto 0)
);
end component;
------------------------------------------------------------------------------
--TX Buffer module
......@@ -367,6 +367,7 @@ package CANcomponents is
signal txt_hw_cmd : out txt_hw_cmd_type;
signal txtb_changed : in std_logic;
signal txt_buf_ptr : out natural range 0 to 19;
signal rec_ident_out : out std_logic_vector(28 downto 0);
signal rec_dlc_out : out std_logic_vector(3 downto 0);
signal rec_ident_type_out : out std_logic;
.....