Commit 9674787f authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '244-separate-mode_settings-command_status' into 'master'

Resolve "Split MODE, SETTINGS, COMMAND, STATUS register"

Closes #244

See merge request !218
parents 0325d86c ede79e4b
This diff is collapsed.
......@@ -139,7 +139,7 @@ u32 ctu_can_fd_get_version(struct ctucanfd_priv *priv)
void ctu_can_fd_enable(struct ctucanfd_priv *priv, bool enable)
{
union ctu_can_fd_mode_command_status_settings reg;
union ctu_can_fd_mode_settings reg;
reg.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
reg.s.ena = enable ? CTU_CAN_ENABLED : CTU_CAN_DISABLED;
......@@ -148,7 +148,7 @@ void ctu_can_fd_enable(struct ctucanfd_priv *priv, bool enable)
void ctu_can_fd_reset(struct ctucanfd_priv *priv)
{
union ctu_can_fd_mode_command_status_settings mode;
union ctu_can_fd_mode_settings mode;
mode.u32 = 0;
mode.s.rst = 1;
......@@ -160,7 +160,7 @@ void ctu_can_fd_reset(struct ctucanfd_priv *priv)
bool ctu_can_fd_set_ret_limit(struct ctucanfd_priv *priv, bool enable, u8 limit)
{
union ctu_can_fd_mode_command_status_settings reg;
union ctu_can_fd_mode_settings reg;
if (limit > CTU_CAN_FD_RETR_MAX)
return false;
......@@ -176,7 +176,7 @@ void ctu_can_fd_set_mode_reg(struct ctucanfd_priv *priv,
const struct can_ctrlmode *mode)
{
u32 flags = mode->flags;
union ctu_can_fd_mode_command_status_settings reg;
union ctu_can_fd_mode_settings reg;
reg.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
......@@ -211,29 +211,29 @@ void ctu_can_fd_set_mode_reg(struct ctucanfd_priv *priv,
void ctu_can_fd_rel_rx_buf(struct ctucanfd_priv *priv)
{
union ctu_can_fd_mode_command_status_settings reg;
union ctu_can_fd_command reg;
reg.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
reg.u32 = 0;
reg.s.rrb = 1;
priv->write_reg(priv, CTU_CAN_FD_MODE, reg.u32);
priv->write_reg(priv, CTU_CAN_FD_COMMAND, reg.u32);
}
void ctu_can_fd_clr_overrun_flag(struct ctucanfd_priv *priv)
{
union ctu_can_fd_mode_command_status_settings reg;
union ctu_can_fd_command reg;
reg.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
reg.u32 = 0;
reg.s.cdo = 1;
priv->write_reg(priv, CTU_CAN_FD_MODE, reg.u32);
priv->write_reg(priv, CTU_CAN_FD_COMMAND, reg.u32);
}
void ctu_can_fd_abort_tx(struct ctucanfd_priv *priv)
{
union ctu_can_fd_mode_command_status_settings reg;
union ctu_can_fd_command reg;
reg.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
reg.u32 = 0;
reg.s.abt = 1;
priv->write_reg(priv, CTU_CAN_FD_MODE, reg.u32);
priv->write_reg(priv, CTU_CAN_FD_COMMAND, reg.u32);
}
// TODO: rather than set(value, mask) interface, provide
......
......@@ -291,13 +291,13 @@ void ctu_can_fd_abort_tx(struct ctucanfd_priv *priv);
* Returns:
* Mode/status structure with multiple mode flags.
*/
static inline union ctu_can_fd_mode_command_status_settings
static inline union ctu_can_fd_status
ctu_can_get_status(struct ctucanfd_priv *priv)
{
/* MODE and STATUS are within the same word */
union ctu_can_fd_mode_command_status_settings res;
union ctu_can_fd_status res;
res.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
res.u32 = priv->read_reg(priv, CTU_CAN_FD_STATUS);
return res;
}
......@@ -313,7 +313,7 @@ static inline union ctu_can_fd_mode_command_status_settings
*/
static inline bool ctu_can_fd_is_enabled(struct ctucanfd_priv *priv)
{
union ctu_can_fd_mode_command_status_settings reg;
union ctu_can_fd_mode_settings reg;
reg.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
return reg.s.ena == CTU_CAN_ENABLED;
......
......@@ -43,52 +43,52 @@ enum ctu_can_fd_can_registers {
CTU_CAN_FD_DEVICE_ID = 0x0,
CTU_CAN_FD_VERSION = 0x2,
CTU_CAN_FD_MODE = 0x4,
CTU_CAN_FD_COMMAND = 0x5,
CTU_CAN_FD_STATUS = 0x6,
CTU_CAN_FD_SETTINGS = 0x7,
CTU_CAN_FD_INT_STAT = 0x8,
CTU_CAN_FD_INT_ENA_SET = 0xc,
CTU_CAN_FD_INT_ENA_CLR = 0x10,
CTU_CAN_FD_INT_MASK_SET = 0x14,
CTU_CAN_FD_INT_MASK_CLR = 0x18,
CTU_CAN_FD_BTR = 0x1c,
CTU_CAN_FD_BTR_FD = 0x20,
CTU_CAN_FD_EWL = 0x24,
CTU_CAN_FD_ERP = 0x25,
CTU_CAN_FD_FAULT_STATE = 0x26,
CTU_CAN_FD_RXC = 0x28,
CTU_CAN_FD_TXC = 0x2a,
CTU_CAN_FD_ERR_NORM = 0x2c,
CTU_CAN_FD_ERR_FD = 0x2e,
CTU_CAN_FD_CTR_PRES = 0x30,
CTU_CAN_FD_FILTER_A_MASK = 0x34,
CTU_CAN_FD_FILTER_A_VAL = 0x38,
CTU_CAN_FD_FILTER_B_MASK = 0x3c,
CTU_CAN_FD_FILTER_B_VAL = 0x40,
CTU_CAN_FD_FILTER_C_MASK = 0x44,
CTU_CAN_FD_FILTER_C_VAL = 0x48,
CTU_CAN_FD_FILTER_RAN_LOW = 0x4c,
CTU_CAN_FD_FILTER_RAN_HIGH = 0x50,
CTU_CAN_FD_FILTER_CONTROL = 0x54,
CTU_CAN_FD_FILTER_STATUS = 0x56,
CTU_CAN_FD_RX_MEM_INFO = 0x58,
CTU_CAN_FD_RX_POINTERS = 0x5c,
CTU_CAN_FD_RX_STATUS = 0x60,
CTU_CAN_FD_RX_SETTINGS = 0x62,
CTU_CAN_FD_RX_DATA = 0x64,
CTU_CAN_FD_TX_STATUS = 0x68,
CTU_CAN_FD_TX_COMMAND = 0x6c,
CTU_CAN_FD_TX_PRIORITY = 0x70,
CTU_CAN_FD_ERR_CAPT = 0x74,
CTU_CAN_FD_ALC = 0x75,
CTU_CAN_FD_TRV_DELAY = 0x78,
CTU_CAN_FD_SSP_CFG = 0x7a,
CTU_CAN_FD_RX_COUNTER = 0x7c,
CTU_CAN_FD_TX_COUNTER = 0x80,
CTU_CAN_FD_DEBUG_REGISTER = 0x84,
CTU_CAN_FD_YOLO_REG = 0x88,
CTU_CAN_FD_TIMESTAMP_LOW = 0x90,
CTU_CAN_FD_TIMESTAMP_HIGH = 0x94,
CTU_CAN_FD_SETTINGS = 0x6,
CTU_CAN_FD_STATUS = 0x8,
CTU_CAN_FD_COMMAND = 0xc,
CTU_CAN_FD_INT_STAT = 0x10,
CTU_CAN_FD_INT_ENA_SET = 0x14,
CTU_CAN_FD_INT_ENA_CLR = 0x18,
CTU_CAN_FD_INT_MASK_SET = 0x1c,
CTU_CAN_FD_INT_MASK_CLR = 0x20,
CTU_CAN_FD_BTR = 0x24,
CTU_CAN_FD_BTR_FD = 0x28,
CTU_CAN_FD_EWL = 0x2c,
CTU_CAN_FD_ERP = 0x2d,
CTU_CAN_FD_FAULT_STATE = 0x2e,
CTU_CAN_FD_RXC = 0x30,
CTU_CAN_FD_TXC = 0x32,
CTU_CAN_FD_ERR_NORM = 0x34,
CTU_CAN_FD_ERR_FD = 0x36,
CTU_CAN_FD_CTR_PRES = 0x38,
CTU_CAN_FD_FILTER_A_MASK = 0x3c,
CTU_CAN_FD_FILTER_A_VAL = 0x40,
CTU_CAN_FD_FILTER_B_MASK = 0x44,
CTU_CAN_FD_FILTER_B_VAL = 0x48,
CTU_CAN_FD_FILTER_C_MASK = 0x4c,
CTU_CAN_FD_FILTER_C_VAL = 0x50,
CTU_CAN_FD_FILTER_RAN_LOW = 0x54,
CTU_CAN_FD_FILTER_RAN_HIGH = 0x58,
CTU_CAN_FD_FILTER_CONTROL = 0x5c,
CTU_CAN_FD_FILTER_STATUS = 0x5e,
CTU_CAN_FD_RX_MEM_INFO = 0x60,
CTU_CAN_FD_RX_POINTERS = 0x64,
CTU_CAN_FD_RX_STATUS = 0x68,
CTU_CAN_FD_RX_SETTINGS = 0x6a,
CTU_CAN_FD_RX_DATA = 0x6c,
CTU_CAN_FD_TX_STATUS = 0x70,
CTU_CAN_FD_TX_COMMAND = 0x74,
CTU_CAN_FD_TX_PRIORITY = 0x78,
CTU_CAN_FD_ERR_CAPT = 0x7c,
CTU_CAN_FD_ALC = 0x7e,
CTU_CAN_FD_TRV_DELAY = 0x80,
CTU_CAN_FD_SSP_CFG = 0x82,
CTU_CAN_FD_RX_COUNTER = 0x84,
CTU_CAN_FD_TX_COUNTER = 0x88,
CTU_CAN_FD_DEBUG_REGISTER = 0x8c,
CTU_CAN_FD_YOLO_REG = 0x90,
CTU_CAN_FD_TIMESTAMP_LOW = 0x94,
CTU_CAN_FD_TIMESTAMP_HIGH = 0x98,
CTU_CAN_FD_TXTB1_DATA_1 = 0x100,
CTU_CAN_FD_TXTB1_DATA_2 = 0x104,
CTU_CAN_FD_TXTB1_DATA_20 = 0x14c,
......@@ -133,9 +133,9 @@ enum ctu_can_fd_device_id_device_id {
CTU_CAN_FD_ID = 0xcafd,
};
union ctu_can_fd_mode_command_status_settings {
union ctu_can_fd_mode_settings {
uint32_t u32;
struct ctu_can_fd_mode_command_status_settings_s {
struct ctu_can_fd_mode_settings_s {
#ifdef __LITTLE_ENDIAN_BITFIELD
/* MODE */
uint32_t rst : 1;
......@@ -146,52 +146,22 @@ union ctu_can_fd_mode_command_status_settings {
uint32_t rtrp : 1;
uint32_t tsm : 1;
uint32_t acf : 1;
uint32_t reserved_8 : 1;
/* COMMAND */
uint32_t abt : 1;
uint32_t rrb : 1;
uint32_t cdo : 1;
uint32_t ercrst : 1;
uint32_t rxfcrst : 1;
uint32_t txfcrst : 1;
uint32_t reserved_15 : 1;
/* STATUS */
uint32_t rxne : 1;
uint32_t dor : 1;
uint32_t txnf : 1;
uint32_t eft : 1;
uint32_t rxs : 1;
uint32_t txs : 1;
uint32_t ewl : 1;
uint32_t idle : 1;
uint32_t reserved_15_8 : 8;
/* SETTINGS */
uint32_t rtrle : 1;
uint32_t rtrth : 4;
uint32_t ilbp : 1;
uint32_t ena : 1;
uint32_t nisofd : 1;
uint32_t reserved_31_24 : 8;
#else
uint32_t reserved_31_24 : 8;
uint32_t nisofd : 1;
uint32_t ena : 1;
uint32_t ilbp : 1;
uint32_t rtrth : 4;
uint32_t rtrle : 1;
uint32_t idle : 1;
uint32_t ewl : 1;
uint32_t txs : 1;
uint32_t rxs : 1;
uint32_t eft : 1;
uint32_t txnf : 1;
uint32_t dor : 1;
uint32_t rxne : 1;
uint32_t reserved_15 : 1;
uint32_t txfcrst : 1;
uint32_t rxfcrst : 1;
uint32_t ercrst : 1;
uint32_t cdo : 1;
uint32_t rrb : 1;
uint32_t abt : 1;
uint32_t reserved_8 : 1;
uint32_t reserved_15_8 : 8;
uint32_t acf : 1;
uint32_t tsm : 1;
uint32_t rtrp : 1;
......@@ -259,6 +229,60 @@ enum ctu_can_fd_settings_nisofd {
NON_ISO_FD = 0x1,
};
union ctu_can_fd_status {
uint32_t u32;
struct ctu_can_fd_status_s {
#ifdef __LITTLE_ENDIAN_BITFIELD
/* STATUS */
uint32_t rxne : 1;
uint32_t dor : 1;
uint32_t txnf : 1;
uint32_t eft : 1;
uint32_t rxs : 1;
uint32_t txs : 1;
uint32_t ewl : 1;
uint32_t idle : 1;
uint32_t reserved_31_8 : 24;
#else
uint32_t reserved_31_8 : 24;
uint32_t idle : 1;
uint32_t ewl : 1;
uint32_t txs : 1;
uint32_t rxs : 1;
uint32_t eft : 1;
uint32_t txnf : 1;
uint32_t dor : 1;
uint32_t rxne : 1;
#endif
} s;
};
union ctu_can_fd_command {
uint32_t u32;
struct ctu_can_fd_command_s {
#ifdef __LITTLE_ENDIAN_BITFIELD
uint32_t reserved_0 : 1;
/* COMMAND */
uint32_t abt : 1;
uint32_t rrb : 1;
uint32_t cdo : 1;
uint32_t ercrst : 1;
uint32_t rxfcrst : 1;
uint32_t txfcrst : 1;
uint32_t reserved_31_7 : 25;
#else
uint32_t reserved_31_7 : 25;
uint32_t txfcrst : 1;
uint32_t rxfcrst : 1;
uint32_t ercrst : 1;
uint32_t cdo : 1;
uint32_t rrb : 1;
uint32_t abt : 1;
uint32_t reserved_0 : 1;
#endif
} s;
};
union ctu_can_fd_int_stat {
uint32_t u32;
struct ctu_can_fd_int_stat_s {
......@@ -803,14 +827,16 @@ union ctu_can_fd_err_capt_alc {
/* ERR_CAPT */
uint32_t err_pos : 5;
uint32_t err_type : 3;
uint32_t reserved_15_8 : 8;
/* ALC */
uint32_t alc_bit : 5;
uint32_t alc_id_field : 3;
uint32_t reserved_31_16 : 16;
uint32_t reserved_31_24 : 8;
#else
uint32_t reserved_31_16 : 16;
uint32_t reserved_31_24 : 8;
uint32_t alc_id_field : 3;
uint32_t alc_bit : 5;
uint32_t reserved_15_8 : 8;
uint32_t err_type : 3;
uint32_t err_pos : 5;
#endif
......
......@@ -252,8 +252,8 @@ int main(int argc, char *argv[])
addrs[0] = pci_find_bar(0x1172, 0xcafd, 0, 1);
if (!addrs[0])
addrs[0] = pci_find_bar(0x1760, 0xff00, 0, 1);
if (!addrs[0])
err(1, "-p PCI device not found");
if (!addrs[0])
err(1, "-p PCI device not found");
addrs[1] = addrs[0] + 0x4000;
break;
case 'h':
......@@ -323,7 +323,7 @@ int main(int argc, char *argv[])
ctu_can_fd_reset(priv);
{
union ctu_can_fd_mode_command_status_settings mode;
union ctu_can_fd_mode_settings mode;
mode.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
if (mode.s.ena) {
......@@ -423,8 +423,8 @@ int main(int argc, char *argv[])
u32 rxsz = reg.s.rx_buff_size - reg.s.rx_mem_free;
printf("%u RX frames, %u words", nrxf, rxsz);
printf(", status 0x%02hhx", ctu_can_fd_read8(priv, CTU_CAN_FD_STATUS));
printf(", settings 0x%02hhx", ctu_can_fd_read8(priv, CTU_CAN_FD_SETTINGS));
printf(", status 0x%08hhx", ctu_can_fd_read32(priv, CTU_CAN_FD_STATUS));
printf(", settings 0x%04hhx", ctu_can_fd_read16(priv, CTU_CAN_FD_SETTINGS));
printf(", INT_STAT 0x%04hhx", ctu_can_fd_read16(priv, CTU_CAN_FD_INT_STAT));
printf(", INT_ENA_SET 0x%04hx", priv->read_reg(priv, CTU_CAN_FD_INT_ENA_SET));
printf(", INT_MASK_SET 0x%04hx", priv->read_reg(priv, CTU_CAN_FD_INT_MASK_SET));
......
......@@ -59,52 +59,52 @@ package can_fd_register_map is
constant DEVICE_ID_ADR : std_logic_vector(11 downto 0) := x"000";
constant VERSION_ADR : std_logic_vector(11 downto 0) := x"002";
constant MODE_ADR : std_logic_vector(11 downto 0) := x"004";
constant COMMAND_ADR : std_logic_vector(11 downto 0) := x"005";
constant STATUS_ADR : std_logic_vector(11 downto 0) := x"006";
constant SETTINGS_ADR : std_logic_vector(11 downto 0) := x"007";
constant INT_STAT_ADR : std_logic_vector(11 downto 0) := x"008";
constant INT_ENA_SET_ADR : std_logic_vector(11 downto 0) := x"00C";
constant INT_ENA_CLR_ADR : std_logic_vector(11 downto 0) := x"010";
constant INT_MASK_SET_ADR : std_logic_vector(11 downto 0) := x"014";
constant INT_MASK_CLR_ADR : std_logic_vector(11 downto 0) := x"018";
constant BTR_ADR : std_logic_vector(11 downto 0) := x"01C";
constant BTR_FD_ADR : std_logic_vector(11 downto 0) := x"020";
constant EWL_ADR : std_logic_vector(11 downto 0) := x"024";
constant ERP_ADR : std_logic_vector(11 downto 0) := x"025";
constant FAULT_STATE_ADR : std_logic_vector(11 downto 0) := x"026";
constant RXC_ADR : std_logic_vector(11 downto 0) := x"028";
constant TXC_ADR : std_logic_vector(11 downto 0) := x"02A";
constant ERR_NORM_ADR : std_logic_vector(11 downto 0) := x"02C";
constant ERR_FD_ADR : std_logic_vector(11 downto 0) := x"02E";
constant CTR_PRES_ADR : std_logic_vector(11 downto 0) := x"030";
constant FILTER_A_MASK_ADR : std_logic_vector(11 downto 0) := x"034";
constant FILTER_A_VAL_ADR : std_logic_vector(11 downto 0) := x"038";
constant FILTER_B_MASK_ADR : std_logic_vector(11 downto 0) := x"03C";
constant FILTER_B_VAL_ADR : std_logic_vector(11 downto 0) := x"040";
constant FILTER_C_MASK_ADR : std_logic_vector(11 downto 0) := x"044";
constant FILTER_C_VAL_ADR : std_logic_vector(11 downto 0) := x"048";
constant FILTER_RAN_LOW_ADR : std_logic_vector(11 downto 0) := x"04C";
constant FILTER_RAN_HIGH_ADR : std_logic_vector(11 downto 0) := x"050";
constant FILTER_CONTROL_ADR : std_logic_vector(11 downto 0) := x"054";
constant FILTER_STATUS_ADR : std_logic_vector(11 downto 0) := x"056";
constant RX_MEM_INFO_ADR : std_logic_vector(11 downto 0) := x"058";
constant RX_POINTERS_ADR : std_logic_vector(11 downto 0) := x"05C";
constant RX_STATUS_ADR : std_logic_vector(11 downto 0) := x"060";
constant RX_SETTINGS_ADR : std_logic_vector(11 downto 0) := x"062";
constant RX_DATA_ADR : std_logic_vector(11 downto 0) := x"064";
constant TX_STATUS_ADR : std_logic_vector(11 downto 0) := x"068";
constant TX_COMMAND_ADR : std_logic_vector(11 downto 0) := x"06C";
constant TX_PRIORITY_ADR : std_logic_vector(11 downto 0) := x"070";
constant ERR_CAPT_ADR : std_logic_vector(11 downto 0) := x"074";
constant ALC_ADR : std_logic_vector(11 downto 0) := x"075";
constant TRV_DELAY_ADR : std_logic_vector(11 downto 0) := x"078";
constant SSP_CFG_ADR : std_logic_vector(11 downto 0) := x"07A";
constant RX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"07C";
constant TX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"080";
constant DEBUG_REGISTER_ADR : std_logic_vector(11 downto 0) := x"084";
constant YOLO_REG_ADR : std_logic_vector(11 downto 0) := x"088";
constant TIMESTAMP_LOW_ADR : std_logic_vector(11 downto 0) := x"090";
constant TIMESTAMP_HIGH_ADR : std_logic_vector(11 downto 0) := x"094";
constant SETTINGS_ADR : std_logic_vector(11 downto 0) := x"006";
constant STATUS_ADR : std_logic_vector(11 downto 0) := x"008";
constant COMMAND_ADR : std_logic_vector(11 downto 0) := x"00C";
constant INT_STAT_ADR : std_logic_vector(11 downto 0) := x"010";
constant INT_ENA_SET_ADR : std_logic_vector(11 downto 0) := x"014";
constant INT_ENA_CLR_ADR : std_logic_vector(11 downto 0) := x"018";
constant INT_MASK_SET_ADR : std_logic_vector(11 downto 0) := x"01C";
constant INT_MASK_CLR_ADR : std_logic_vector(11 downto 0) := x"020";
constant BTR_ADR : std_logic_vector(11 downto 0) := x"024";
constant BTR_FD_ADR : std_logic_vector(11 downto 0) := x"028";
constant EWL_ADR : std_logic_vector(11 downto 0) := x"02C";
constant ERP_ADR : std_logic_vector(11 downto 0) := x"02D";
constant FAULT_STATE_ADR : std_logic_vector(11 downto 0) := x"02E";
constant RXC_ADR : std_logic_vector(11 downto 0) := x"030";
constant TXC_ADR : std_logic_vector(11 downto 0) := x"032";
constant ERR_NORM_ADR : std_logic_vector(11 downto 0) := x"034";
constant ERR_FD_ADR : std_logic_vector(11 downto 0) := x"036";
constant CTR_PRES_ADR : std_logic_vector(11 downto 0) := x"038";
constant FILTER_A_MASK_ADR : std_logic_vector(11 downto 0) := x"03C";
constant FILTER_A_VAL_ADR : std_logic_vector(11 downto 0) := x"040";
constant FILTER_B_MASK_ADR : std_logic_vector(11 downto 0) := x"044";
constant FILTER_B_VAL_ADR : std_logic_vector(11 downto 0) := x"048";
constant FILTER_C_MASK_ADR : std_logic_vector(11 downto 0) := x"04C";
constant FILTER_C_VAL_ADR : std_logic_vector(11 downto 0) := x"050";
constant FILTER_RAN_LOW_ADR : std_logic_vector(11 downto 0) := x"054";
constant FILTER_RAN_HIGH_ADR : std_logic_vector(11 downto 0) := x"058";
constant FILTER_CONTROL_ADR : std_logic_vector(11 downto 0) := x"05C";
constant FILTER_STATUS_ADR : std_logic_vector(11 downto 0) := x"05E";
constant RX_MEM_INFO_ADR : std_logic_vector(11 downto 0) := x"060";
constant RX_POINTERS_ADR : std_logic_vector(11 downto 0) := x"064";
constant RX_STATUS_ADR : std_logic_vector(11 downto 0) := x"068";
constant RX_SETTINGS_ADR : std_logic_vector(11 downto 0) := x"06A";
constant RX_DATA_ADR : std_logic_vector(11 downto 0) := x"06C";
constant TX_STATUS_ADR : std_logic_vector(11 downto 0) := x"070";
constant TX_COMMAND_ADR : std_logic_vector(11 downto 0) := x"074";
constant TX_PRIORITY_ADR : std_logic_vector(11 downto 0) := x"078";
constant ERR_CAPT_ADR : std_logic_vector(11 downto 0) := x"07C";
constant ALC_ADR : std_logic_vector(11 downto 0) := x"07E";
constant TRV_DELAY_ADR : std_logic_vector(11 downto 0) := x"080";
constant SSP_CFG_ADR : std_logic_vector(11 downto 0) := x"082";
constant RX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"084";
constant TX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"088";
constant DEBUG_REGISTER_ADR : std_logic_vector(11 downto 0) := x"08C";
constant YOLO_REG_ADR : std_logic_vector(11 downto 0) := x"090";
constant TIMESTAMP_LOW_ADR : std_logic_vector(11 downto 0) := x"094";
constant TIMESTAMP_HIGH_ADR : std_logic_vector(11 downto 0) := x"098";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......@@ -244,64 +244,18 @@ package can_fd_register_map is
constant STM_RSTVAL : std_logic := '0';
constant AFM_RSTVAL : std_logic := '0';
------------------------------------------------------------------------------
-- COMMAND register
--
-- Writing logic 1 into each bit gives different command to the IP Core. After
-- writing logic 1, logic 0 does not have to be written.
------------------------------------------------------------------------------
constant ABT_IND : natural := 9;
constant RRB_IND : natural := 10;
constant CDO_IND : natural := 11;
constant ERCRST_IND : natural := 12;
constant RXFCRST_IND : natural := 13;
constant TXFCRST_IND : natural := 14;
-- COMMAND register reset values
constant ABT_RSTVAL : std_logic := '0';
constant RRB_RSTVAL : std_logic := '0';
constant CDO_RSTVAL : std_logic := '0';
constant ERCRST_RSTVAL : std_logic := '0';
constant RXFCRST_RSTVAL : std_logic := '0';
constant TXFCRST_RSTVAL : std_logic := '0';
------------------------------------------------------------------------------
-- STATUS register
--
-- Register signals various states of CTU CAN FD IP Core. Logic 1 signals acti
-- ve status/flag.
------------------------------------------------------------------------------
constant RXNE_IND : natural := 16;
constant DOR_IND : natural := 17;
constant TXNF_IND : natural := 18;
constant EFT_IND : natural := 19;
constant RXS_IND : natural := 20;
constant TXS_IND : natural := 21;
constant EWL_IND : natural := 22;
constant IDLE_IND : natural := 23;
-- STATUS register reset values
constant RXNE_RSTVAL : std_logic := '0';
constant TXNF_RSTVAL : std_logic := '0';
constant DOR_RSTVAL : std_logic := '0';
constant EFT_RSTVAL : std_logic := '0';
constant RXS_RSTVAL : std_logic := '0';
constant TXS_RSTVAL : std_logic := '0';
constant EWL_RSTVAL : std_logic := '0';
constant IDLE_RSTVAL : std_logic := '1';
------------------------------------------------------------------------------
-- SETTINGS register
--
-- This register enables the whole CAN FD Core, configures FD Type, Internal l
-- oopback and retransmission options.
------------------------------------------------------------------------------
constant RTRLE_IND : natural := 24;
constant RTRTH_L : natural := 25;
constant RTRTH_H : natural := 28;
constant ILBP_IND : natural := 29;
constant ENA_IND : natural := 30;
constant NISOFD_IND : natural := 31;
constant RTRLE_IND : natural := 16;
constant RTRTH_L : natural := 17;
constant RTRTH_H : natural := 20;
constant ILBP_IND : natural := 21;
constant ENA_IND : natural := 22;
constant NISOFD_IND : natural := 23;
-- "RTRLE" field enumerated values
constant RTRLE_DISABLED : std_logic := '0';
......@@ -326,6 +280,52 @@ package can_fd_register_map is
constant ENA_RSTVAL : std_logic := '0';
constant NISOFD_RSTVAL : std_logic := '0';
------------------------------------------------------------------------------
-- STATUS register
--
-- Register signals various states of CTU CAN FD IP Core. Logic 1 signals acti
-- ve status/flag.
------------------------------------------------------------------------------
constant RXNE_IND : natural := 0;
constant DOR_IND : natural := 1;
constant TXNF_IND : natural := 2;
constant EFT_IND : natural := 3;
constant RXS_IND : natural := 4;
constant TXS_IND : natural := 5;
constant EWL_IND : natural := 6;
constant IDLE_IND : natural := 7;
-- STATUS register reset values
constant RXNE_RSTVAL : std_logic := '0';
constant TXNF_RSTVAL : std_logic := '0';
constant DOR_RSTVAL : std_logic := '0';
constant EFT_RSTVAL : std_logic := '0';
constant RXS_RSTVAL : std_logic := '0';
constant TXS_RSTVAL : std_logic := '0';
constant EWL_RSTVAL : std_logic := '0';
constant IDLE_RSTVAL : std_logic := '1';
------------------------------------------------------------------------------
-- COMMAND register
--
-- Writing logic 1 into each bit gives different command to the IP Core. After
-- writing logic 1, logic 0 does not have to be written.
------------------------------------------------------------------------------
constant ABT_IND : natural := 1;
constant RRB_IND : natural := 2;
constant CDO_IND : natural := 3;
constant ERCRST_IND : natural := 4;
constant RXFCRST_IND : natural := 5;
constant TXFCRST_IND : natural := 6;