Commit 901a996a authored by Pavel Pisa's avatar Pavel Pisa Committed by Ille, Ondrej, Ing.

register_map: update generated files after MODE, SETTINGS, COMMAND, STATUS split.

Signed-off-by: Pavel Pisa's avatarPavel Pisa <pisa@cmp.felk.cvut.cz>
parent 29a8f5a7
This diff is collapsed.
......@@ -43,50 +43,50 @@ enum ctu_can_fd_can_registers {
CTU_CAN_FD_DEVICE_ID = 0x0,
CTU_CAN_FD_VERSION = 0x2,
CTU_CAN_FD_MODE = 0x4,
CTU_CAN_FD_COMMAND = 0x5,
CTU_CAN_FD_STATUS = 0x6,
CTU_CAN_FD_SETTINGS = 0x7,
CTU_CAN_FD_INT_STAT = 0x8,
CTU_CAN_FD_INT_ENA_SET = 0xc,
CTU_CAN_FD_INT_ENA_CLR = 0x10,
CTU_CAN_FD_INT_MASK_SET = 0x14,
CTU_CAN_FD_INT_MASK_CLR = 0x18,
CTU_CAN_FD_BTR = 0x1c,
CTU_CAN_FD_BTR_FD = 0x20,
CTU_CAN_FD_EWL = 0x24,
CTU_CAN_FD_ERP = 0x25,
CTU_CAN_FD_FAULT_STATE = 0x26,
CTU_CAN_FD_RXC = 0x28,
CTU_CAN_FD_TXC = 0x2a,
CTU_CAN_FD_ERR_NORM = 0x2c,
CTU_CAN_FD_ERR_FD = 0x2e,
CTU_CAN_FD_CTR_PRES = 0x30,
CTU_CAN_FD_FILTER_A_MASK = 0x34,
CTU_CAN_FD_FILTER_A_VAL = 0x38,
CTU_CAN_FD_FILTER_B_MASK = 0x3c,
CTU_CAN_FD_FILTER_B_VAL = 0x40,
CTU_CAN_FD_FILTER_C_MASK = 0x44,
CTU_CAN_FD_FILTER_C_VAL = 0x48,
CTU_CAN_FD_FILTER_RAN_LOW = 0x4c,
CTU_CAN_FD_FILTER_RAN_HIGH = 0x50,
CTU_CAN_FD_FILTER_CONTROL = 0x54,
CTU_CAN_FD_FILTER_STATUS = 0x56,
CTU_CAN_FD_RX_MEM_INFO = 0x58,
CTU_CAN_FD_RX_POINTERS = 0x5c,
CTU_CAN_FD_RX_STATUS = 0x60,
CTU_CAN_FD_RX_SETTINGS = 0x62,
CTU_CAN_FD_RX_DATA = 0x64,
CTU_CAN_FD_TX_STATUS = 0x68,
CTU_CAN_FD_TX_COMMAND = 0x6c,
CTU_CAN_FD_TX_PRIORITY = 0x70,
CTU_CAN_FD_ERR_CAPT = 0x74,
CTU_CAN_FD_ALC = 0x75,
CTU_CAN_FD_TRV_DELAY = 0x78,
CTU_CAN_FD_SSP_CFG = 0x7a,
CTU_CAN_FD_RX_COUNTER = 0x7c,
CTU_CAN_FD_TX_COUNTER = 0x80,
CTU_CAN_FD_DEBUG_REGISTER = 0x84,
CTU_CAN_FD_YOLO_REG = 0x88,
CTU_CAN_FD_SETTINGS = 0x6,
CTU_CAN_FD_STATUS = 0x8,
CTU_CAN_FD_COMMAND = 0xa,
CTU_CAN_FD_INT_STAT = 0xc,
CTU_CAN_FD_INT_ENA_SET = 0x10,
CTU_CAN_FD_INT_ENA_CLR = 0x14,
CTU_CAN_FD_INT_MASK_SET = 0x18,
CTU_CAN_FD_INT_MASK_CLR = 0x1c,
CTU_CAN_FD_BTR = 0x20,
CTU_CAN_FD_BTR_FD = 0x24,
CTU_CAN_FD_EWL = 0x28,
CTU_CAN_FD_ERP = 0x29,
CTU_CAN_FD_FAULT_STATE = 0x2a,
CTU_CAN_FD_RXC = 0x2c,
CTU_CAN_FD_TXC = 0x2e,
CTU_CAN_FD_ERR_NORM = 0x30,
CTU_CAN_FD_ERR_FD = 0x32,
CTU_CAN_FD_CTR_PRES = 0x34,
CTU_CAN_FD_FILTER_A_MASK = 0x38,
CTU_CAN_FD_FILTER_A_VAL = 0x3c,
CTU_CAN_FD_FILTER_B_MASK = 0x40,
CTU_CAN_FD_FILTER_B_VAL = 0x44,
CTU_CAN_FD_FILTER_C_MASK = 0x48,
CTU_CAN_FD_FILTER_C_VAL = 0x4c,
CTU_CAN_FD_FILTER_RAN_LOW = 0x50,
CTU_CAN_FD_FILTER_RAN_HIGH = 0x54,
CTU_CAN_FD_FILTER_CONTROL = 0x58,
CTU_CAN_FD_FILTER_STATUS = 0x5a,
CTU_CAN_FD_RX_MEM_INFO = 0x5c,
CTU_CAN_FD_RX_POINTERS = 0x60,
CTU_CAN_FD_RX_STATUS = 0x64,
CTU_CAN_FD_RX_SETTINGS = 0x66,
CTU_CAN_FD_RX_DATA = 0x68,
CTU_CAN_FD_TX_STATUS = 0x6c,
CTU_CAN_FD_TX_COMMAND = 0x70,
CTU_CAN_FD_TX_PRIORITY = 0x74,
CTU_CAN_FD_ERR_CAPT = 0x78,
CTU_CAN_FD_ALC = 0x79,
CTU_CAN_FD_TRV_DELAY = 0x7c,
CTU_CAN_FD_SSP_CFG = 0x7e,
CTU_CAN_FD_RX_COUNTER = 0x80,
CTU_CAN_FD_TX_COUNTER = 0x84,
CTU_CAN_FD_DEBUG_REGISTER = 0x88,
CTU_CAN_FD_YOLO_REG = 0x8c,
CTU_CAN_FD_TIMESTAMP_LOW = 0x90,
CTU_CAN_FD_TIMESTAMP_HIGH = 0x94,
CTU_CAN_FD_TXTB1_DATA_1 = 0x100,
......@@ -133,9 +133,9 @@ enum ctu_can_fd_device_id_device_id {
CTU_CAN_FD_ID = 0xcafd,
};
union ctu_can_fd_mode_command_status_settings {
union ctu_can_fd_mode_settings {
uint32_t u32;
struct ctu_can_fd_mode_command_status_settings_s {
struct ctu_can_fd_mode_settings_s {
#ifdef __LITTLE_ENDIAN_BITFIELD
/* MODE */
uint32_t rst : 1;
......@@ -146,52 +146,22 @@ union ctu_can_fd_mode_command_status_settings {
uint32_t rtrp : 1;
uint32_t tsm : 1;
uint32_t acf : 1;
uint32_t reserved_8 : 1;
/* COMMAND */
uint32_t abt : 1;
uint32_t rrb : 1;
uint32_t cdo : 1;
uint32_t ercrst : 1;
uint32_t rxfcrst : 1;
uint32_t txfcrst : 1;
uint32_t reserved_15 : 1;
/* STATUS */
uint32_t rxne : 1;
uint32_t dor : 1;
uint32_t txnf : 1;
uint32_t eft : 1;
uint32_t rxs : 1;
uint32_t txs : 1;
uint32_t ewl : 1;
uint32_t idle : 1;
uint32_t reserved_15_8 : 8;
/* SETTINGS */
uint32_t rtrle : 1;
uint32_t rtrth : 4;
uint32_t ilbp : 1;
uint32_t ena : 1;
uint32_t nisofd : 1;
uint32_t reserved_31_24 : 8;
#else
uint32_t reserved_31_24 : 8;
uint32_t nisofd : 1;
uint32_t ena : 1;
uint32_t ilbp : 1;
uint32_t rtrth : 4;
uint32_t rtrle : 1;
uint32_t idle : 1;
uint32_t ewl : 1;
uint32_t txs : 1;
uint32_t rxs : 1;
uint32_t eft : 1;
uint32_t txnf : 1;
uint32_t dor : 1;
uint32_t rxne : 1;
uint32_t reserved_15 : 1;
uint32_t txfcrst : 1;
uint32_t rxfcrst : 1;
uint32_t ercrst : 1;
uint32_t cdo : 1;
uint32_t rrb : 1;
uint32_t abt : 1;
uint32_t reserved_8 : 1;
uint32_t reserved_15_8 : 8;
uint32_t acf : 1;
uint32_t tsm : 1;
uint32_t rtrp : 1;
......@@ -259,6 +229,49 @@ enum ctu_can_fd_settings_nisofd {
NON_ISO_FD = 0x1,
};
union ctu_can_fd_status_command {
uint32_t u32;
struct ctu_can_fd_status_command_s {
#ifdef __LITTLE_ENDIAN_BITFIELD
/* STATUS */
uint32_t rxne : 1;
uint32_t dor : 1;
uint32_t txnf : 1;
uint32_t eft : 1;
uint32_t rxs : 1;
uint32_t txs : 1;
uint32_t ewl : 1;
uint32_t idle : 1;
uint32_t reserved_16_8 : 9;
/* COMMAND */
uint32_t abt : 1;
uint32_t rrb : 1;
uint32_t cdo : 1;
uint32_t ercrst : 1;
uint32_t rxfcrst : 1;
uint32_t txfcrst : 1;
uint32_t reserved_31_23 : 9;
#else
uint32_t reserved_31_23 : 9;
uint32_t txfcrst : 1;
uint32_t rxfcrst : 1;
uint32_t ercrst : 1;
uint32_t cdo : 1;
uint32_t rrb : 1;
uint32_t abt : 1;
uint32_t reserved_16_8 : 9;
uint32_t idle : 1;
uint32_t ewl : 1;
uint32_t txs : 1;
uint32_t rxs : 1;
uint32_t eft : 1;
uint32_t txnf : 1;
uint32_t dor : 1;
uint32_t rxne : 1;
#endif
} s;
};
union ctu_can_fd_int_stat {
uint32_t u32;
struct ctu_can_fd_int_stat_s {
......
This diff is collapsed.
......@@ -51,8 +51,8 @@ package can_registers_pkg is
type Control_registers_out_t is record
mode : std_logic_vector(7 downto 0);
command : std_logic_vector(7 downto 0);
settings : std_logic_vector(7 downto 0);
command : std_logic_vector(15 downto 0);
int_stat : std_logic_vector(15 downto 0);
int_ena_set : std_logic_vector(15 downto 0);
int_ena_clr : std_logic_vector(15 downto 0);
......@@ -83,7 +83,7 @@ package can_registers_pkg is
type Control_registers_in_t is record
device_id : std_logic_vector(15 downto 0);
version : std_logic_vector(15 downto 0);
status : std_logic_vector(7 downto 0);
status : std_logic_vector(15 downto 0);
int_stat : std_logic_vector(15 downto 0);
int_ena_set : std_logic_vector(15 downto 0);
int_mask_set : std_logic_vector(15 downto 0);
......
......@@ -136,7 +136,7 @@ architecture rtl of data_mux is
-- Data after saturation. Saturated data return all zeroes when address overflow
-- and read beyond last address of register block occurs.
signal saturated_data : std_logic_vector(data_out_width - 1 downto 0);
signal saturated_data : std_logic_vector(data_out_width - 1 downto 0);
-- Data output from data mux (after masking and saturation)
signal masked_data : std_logic_vector(data_out_width - 1 downto 0);
......@@ -150,6 +150,10 @@ architecture rtl of data_mux is
-- Saturated value of internal index.
signal index_sat : natural range 0 to INDEX_MAX;
-- Signals that input address is has overflown the dimension of read array and
-- that zeroes should be returned
signal address_overflow : std_logic;
begin
......@@ -158,7 +162,12 @@ begin
---------------------------------------------------------------------------
index <= to_integer(unsigned(data_selector));
---------------------------------------------------------------------------
-- Signal overflow of address beyond the dimension of read data.
---------------------------------------------------------------------------
address_overflow <= '0' when (index <= INDEX_MAX) else
'1';
---------------------------------------------------------------------------
-- Data selector saturation, we need to saturate data selector in case
-- we don't have 2^N inputs. Address conversion of n bit vector to index
......@@ -166,7 +175,8 @@ begin
-- modulo is not effective, modulo by non 2^N number results in extra
-- shitty logic...
---------------------------------------------------------------------------
index_sat <= index when (index <= INDEX_MAX) else
index_sat <= index when (address_overflow = '0')
else
INDEX_MAX;
......@@ -182,7 +192,7 @@ begin
-- Data saturation
---------------------------------------------------------------------------
data_saturation_gen : for i in 0 to data_out_width - 1 generate
saturated_data(i) <= sel_data(i) when (index <= INDEX_MAX)
saturated_data(i) <= sel_data(i) when (address_overflow = '0')
else
'0';
end generate data_saturation_gen;
......
......@@ -54,35 +54,35 @@ use work.cmn_reg_map_pkg.all;
entity event_logger_reg_map is
generic (
constant DATA_WIDTH : natural := 32;
constant ADDRESS_WIDTH : natural := 8;
constant REGISTERED_READ : boolean := true;
constant CLEAR_READ_DATA : boolean := true;
constant RESET_POLARITY : std_logic := '0'
constant REGISTERED_READ : boolean := true;
constant RESET_POLARITY : std_logic := '0';
constant ADDRESS_WIDTH : natural := 8
);
port (
signal clk_sys :in std_logic;
signal res_n :in std_logic;
signal address :in std_logic_vector(address_width - 1 downto 0);
signal w_data :in std_logic_vector(data_width - 1 downto 0);
signal r_data :out std_logic_vector(data_width - 1 downto 0);
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal cs :in std_logic;
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal event_logger_out :out Event_Logger_out_t;
signal event_logger_in :in Event_Logger_in_t
signal address :in std_logic_vector(address_width - 1 downto 0);
signal read :in std_logic;
signal event_logger_in :in Event_Logger_in_t;
signal r_data :out std_logic_vector(data_width - 1 downto 0);
signal event_logger_out :out Event_Logger_out_t
);
end entity event_logger_reg_map;
architecture rtl of event_logger_reg_map is
signal reg_sel : std_logic_vector(5 downto 0);
constant ADDR_VECT
: std_logic_vector(35 downto 0) := "000101000100000011000010000001000000";
signal read_data_mux_in : std_logic_vector(191 downto 0);
signal read_data_mask_n : std_logic_vector(31 downto 0);
signal event_logger_out_i : Event_Logger_out_t;
signal reg_sel : std_logic_vector(5 downto 0);
signal read_mux_ena : std_logic;
signal event_logger_out_i : Event_Logger_out_t;
signal read_data_mask_n : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------------------------
......@@ -91,18 +91,18 @@ begin
address_decoder_event_logger_comp : address_decoder
generic map(
address_width => 6 ,
registered_out => false ,
address_entries => 6 ,
addr_vect => ADDR_VECT ,
registered_out => false ,
address_width => 6 ,
reset_polarity => RESET_POLARITY
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
address => address(7 downto 2) ,-- in
enable => cs ,-- in
addr_dec => reg_sel -- out
addr_dec => reg_sel ,-- out
address => address(7 downto 2) -- in
);
----------------------------------------------------------------------------
......@@ -112,17 +112,17 @@ begin
log_trig_config_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00000000000000111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000"
auto_clear => "00000000000000000000000000000000" ,
data_mask => "00000000000000111111111111111111" ,
reset_value => "00000000000000000000000000000000"
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(0) ,-- in
write => write ,-- in
data_in => w_data(31 downto 0) ,-- in
w_be => be(3 downto 0) ,-- in
reg_value => event_logger_out_i.log_trig_config -- out
);
......@@ -134,17 +134,17 @@ begin
log_capt_config_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00000000000111111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000"
auto_clear => "00000000000000000000000000000000" ,
data_mask => "00000000000111111111111111111111" ,
reset_value => "00000000000000000000000000000000"
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(1) ,-- in
write => write ,-- in
data_in => w_data(31 downto 0) ,-- in
w_be => be(3 downto 0) ,-- in
reg_value => event_logger_out_i.log_capt_config -- out
);
......@@ -156,17 +156,17 @@ begin
log_command_reg_comp : memory_reg
generic map(
data_width => 8 ,
data_mask => "00001111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000" ,
auto_clear => "00001111"
auto_clear => "00001111" ,
data_mask => "00001111" ,
reset_value => "00000000"
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(7 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(3) ,-- in
write => write ,-- in
data_in => w_data(7 downto 0) ,-- in
w_be => be(0 downto 0) ,-- in
reg_value => event_logger_out_i.log_command -- out
);
......@@ -188,20 +188,20 @@ begin
data_mux_event_logger_comp : data_mux
generic map(
registered_out => REGISTERED_READ ,
data_out_width => 32 ,
data_in_width => 192 ,
reset_polarity => RESET_POLARITY ,
sel_width => 6 ,
registered_out => REGISTERED_READ ,
reset_polarity => RESET_POLARITY
data_in_width => 192
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
enable => read_mux_ena ,-- in
data_selector => address(7 downto 2) ,-- in
data_in => read_data_mux_in ,-- in
data_mask_n => read_data_mask_n ,-- in
enable => read_mux_ena ,-- in
data_out => r_data -- out
data_out => r_data ,-- out
data_mask_n => read_data_mask_n -- in
);
------------------------------------------------------------------------------
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment