Removed "bit_err_enable" since it is unused.

Bit error detection is always enabled in BusSync
and it is validated by Fault conf in Control, CRC and
Data fields! In arbitration this is detected by
protocol control itself!

src/CAN_Core/core_top.vhd

@@ -318,7 +318,6 @@ entity core_top is
     signal sp_control_int          :     std_logic_vector(1 downto 0);
     signal ssp_reset_int           :     std_logic;
     signal trv_delay_calib_int     :     std_logic;
-    signal bit_err_enable_int      :     std_logic;
 
     -- Synchronisation control signal
     signal sync_control_int        :     std_logic_vector(1 downto 0);
@@ -698,7 +697,6 @@ begin
             sp_control         =>  sp_control_int,
             ssp_reset          =>  ssp_reset_int,
             trv_delay_calib    =>  trv_delay_calib_int,
-            bit_err_enable     =>  bit_err_enable_int,
 
             sof_pulse          =>  sof_pulse_r
         );

src/CAN_Core/protocolControl.vhd

@@ -418,11 +418,6 @@ entity protocolControl is
     --Calibration command for transciever delay compenstation (counter)
     signal trv_delay_calib        :out  std_logic;
     
-    --Bit Error detection enable (Ex. disabled when recieving data)
-    signal bit_err_enable         :out  std_logic;
-    --Note: In the end bit Error detection is always enabled, Fault confinement 
-    -- module decides whenever the bit Error is VALID!!!
-    
     --Synchronisation edge validated by prescaler!!!
     signal hard_sync_edge         :in   std_logic;
     
@@ -514,7 +509,6 @@ entity protocolControl is
   signal trv_delay_calib_r        :     std_logic;
   
   --Bit Error detection enable (Ex. disabled when recieving data)
-  signal bit_err_enable_r         :     std_logic;
   signal sync_control_r           :     std_logic_vector(1 downto 0);
   signal alc_r                    :     std_logic_vector(7 downto 0);
 
@@ -782,7 +776,6 @@ begin
   sp_control            <=  sp_control_r;
   ssp_reset             <=  ssp_reset_r;
   trv_delay_calib       <=  trv_delay_calib_r;
-  bit_err_enable        <=  bit_err_enable_r;
   --Synchronisation control
   sync_control          <=  sync_control_r;
   
@@ -1001,7 +994,6 @@ begin
         sp_control_r            <=  NOMINAL_SAMPLE;
         ssp_reset_r             <=  '0';
         trv_delay_calib_r       <=  '0';
-        bit_err_enable_r        <=  '0';
         fixed_CRC_FD            <=  '0';
         fixed_CRC_FD_rec        <=  '0';
         sync_control_r          <=  NO_SYNC;
@@ -1143,7 +1135,6 @@ begin
         sp_control_r           <=  sp_control_r;
         ssp_reset_r            <=  '0';
         trv_delay_calib_r      <=  trv_delay_calib_r;
-        bit_err_enable_r       <=  bit_err_enable_r;
 
         sync_control_r         <=  sync_control_r;
 
@@ -1294,7 +1285,6 @@ begin
 
             -- Bus synchronisation settings
             sp_control_r              <=  NOMINAL_SAMPLE;
-            bit_err_enable_r          <=  '1';
 
             -- Configuration of Bit Destuffing (Both transciever and reciever)
             destuff_enable_r          <=  '1';
@@ -1661,13 +1651,6 @@ begin
             if (FSM_preset = '1') then
                 FSM_preset                      <=  '0';
 
-                ----------------------------------------------------------------
-                -- Enable Bit Error detection. From now on everything that
-                -- we transceive, we must also receive (Either by NOMINAL or
-                -- SECONDARY sampling).
-                ----------------------------------------------------------------
-                bit_err_enable_r                <=  '1';
-
                 ----------------------------------------------------------------
                 -- Calculate real length of data field, which does not
                 -- always correspond to DLC!

src/Libraries/CANcomponents.vhd

@@ -671,7 +671,6 @@ package CANcomponents is
             signal sp_control            : out std_logic_vector(1 downto 0);
             signal ssp_reset             : out std_logic;
             signal trv_delay_calib       : out std_logic;
-            signal bit_err_enable        : out std_logic;
             signal hard_sync_edge        : in  std_logic;
             signal sof_pulse             : out std_logic
         );

test/unit/Protocol_Control/Protocol_Control_tb.vhd

@@ -298,9 +298,6 @@ architecture Protocol_Control_unit_test of CAN_test is
     -- Calibration command for transciever delay compenstation
     signal trv_delay_calib_1        :  std_logic;
 
-    -- Bit Error detection enable (Ex. disabled when recieving data)
-    signal bit_err_enable_1         :  std_logic;
-
     -- Synchronisation edge validated by prescaler!!!
     signal hard_sync_edge_1         :  std_logic;
 
@@ -465,9 +462,6 @@ architecture Protocol_Control_unit_test of CAN_test is
     -- Calibration command for transciever delay compenstation
     signal trv_delay_calib_2        :  std_logic;
 
-    -- Bit Error detection enable (Ex. disabled when recieving data)
-    signal bit_err_enable_2         :  std_logic;
-
     -- Synchronisation edge validated by prescaler!!!
     signal hard_sync_edge_2         :  std_logic;
 
@@ -873,7 +867,6 @@ begin
         sp_control            => sp_control_1,
         ssp_reset             => ssp_reset_1,
         trv_delay_calib       => trv_delay_calib_1,
-        bit_err_enable        => bit_err_enable_1,
         hard_sync_edge        => hard_sync_edge_1,
         sof_pulse             => sof_pulse_1
       );
@@ -948,7 +941,6 @@ begin
         sp_control            => sp_control_2,
         ssp_reset             => ssp_reset_2,
         trv_delay_calib       => trv_delay_calib_2,
-        bit_err_enable        => bit_err_enable_2,
         hard_sync_edge        => hard_sync_edge_2,
         sof_pulse             => sof_pulse_2
       );