Commit 8bc20139 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Merge branch '133-endian-fix' into 'master'

Resolve "Endian fix"

Closes #133

See merge request illeondr/CAN_FD_IP_Core!69
parents 98779f0c 5b8c52e9
......@@ -30,8 +30,8 @@
/* This file is autogenerated, DO NOT EDIT! */
#ifndef __CTU_CAN_FD__
#define __CTU_CAN_FD__
#ifndef __CTU_CAN_FD_FRAME__
#define __CTU_CAN_FD_FRAME__
/* Frame_format memory map */
enum ctu_can_fd_frame_format {
......@@ -49,7 +49,7 @@ enum ctu_can_fd_frame_format {
union ctu_can_fd_frame_form_w {
uint32_t u32;
struct ctu_can_fd_frame_form_w_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FRAME_FORM_W */
uint32_t dlc : 4;
uint32_t reserved_4 : 1;
......@@ -109,7 +109,7 @@ enum ctu_can_fd_frame_form_w_esi_resvd {
union ctu_can_fd_identifier_w {
uint32_t u32;
struct ctu_can_fd_identifier_w_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* IDENTIFIER_W */
uint32_t identifier_ext : 18;
uint32_t identifier_base : 11;
......@@ -141,7 +141,7 @@ union ctu_can_fd_timestamp_u_w {
union ctu_can_fd_data_1_4_w {
uint32_t u32;
struct ctu_can_fd_data_1_4_w_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DATA_1_4_W */
uint32_t data_4 : 8;
uint32_t data_3 : 8;
......@@ -159,7 +159,7 @@ union ctu_can_fd_data_1_4_w {
union ctu_can_fd_data_5_8_w {
uint32_t u32;
struct ctu_can_fd_data_5_8_w_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DATA_5_8_W */
uint32_t data_8 : 8;
uint32_t data_7 : 8;
......@@ -177,7 +177,7 @@ union ctu_can_fd_data_5_8_w {
union ctu_can_fd_data_61_64_w {
uint32_t u32;
struct ctu_can_fd_data_61_64_w_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DATA_61_64_W */
uint32_t data_64 : 8;
uint32_t data_63 : 8;
......
......@@ -30,8 +30,8 @@
/* This file is autogenerated, DO NOT EDIT! */
#ifndef __CTU_CAN_FD__
#define __CTU_CAN_FD__
#ifndef __CTU_CAN_FD_REGS__
#define __CTU_CAN_FD_REGS__
/* Regs memory map */
enum ctu_can_fd_regs {
......@@ -107,7 +107,7 @@ enum ctu_can_fd_regs {
union ctu_can_fd_device_id_version {
uint32_t u32;
struct ctu_can_fd_device_id_version_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DEVICE_ID */
uint32_t device_id : 16;
/* VERSION */
......@@ -128,7 +128,7 @@ enum ctu_can_fd_device_id_device_id {
union ctu_can_fd_mode_command_status_settings {
uint32_t u32;
struct ctu_can_fd_mode_command_status_settings_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* MODE */
uint32_t rst : 1;
uint32_t lom : 1;
......@@ -248,7 +248,7 @@ enum ctu_can_fd_settings_fd_type {
union ctu_can_fd_int_stat {
uint32_t u32;
struct ctu_can_fd_int_stat_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* INT_STAT */
uint32_t ri : 1;
uint32_t ti : 1;
......@@ -284,7 +284,7 @@ union ctu_can_fd_int_stat {
union ctu_can_fd_int_ena_set {
uint32_t u32;
struct ctu_can_fd_int_ena_set_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* INT_ENA_SET */
uint32_t int_ena_set : 12;
uint32_t reserved_31_12 : 20;
......@@ -298,7 +298,7 @@ union ctu_can_fd_int_ena_set {
union ctu_can_fd_int_ena_clr {
uint32_t u32;
struct ctu_can_fd_int_ena_clr_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* INT_ENA_CLR */
uint32_t int_ena_clr : 12;
uint32_t reserved_31_12 : 20;
......@@ -312,7 +312,7 @@ union ctu_can_fd_int_ena_clr {
union ctu_can_fd_int_mask_set {
uint32_t u32;
struct ctu_can_fd_int_mask_set_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* INT_MASK_SET */
uint32_t int_mask_set : 12;
uint32_t reserved_31_12 : 20;
......@@ -326,7 +326,7 @@ union ctu_can_fd_int_mask_set {
union ctu_can_fd_int_mask_clr {
uint32_t u32;
struct ctu_can_fd_int_mask_clr_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* INT_MASK_CLR */
uint32_t int_mask_clr : 12;
uint32_t reserved_31_12 : 20;
......@@ -340,7 +340,7 @@ union ctu_can_fd_int_mask_clr {
union ctu_can_fd_btr {
uint32_t u32;
struct ctu_can_fd_btr_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* BTR */
uint32_t prop : 7;
uint32_t ph1 : 6;
......@@ -360,7 +360,7 @@ union ctu_can_fd_btr {
union ctu_can_fd_btr_fd {
uint32_t u32;
struct ctu_can_fd_btr_fd_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* BTR_FD */
uint32_t prop_fd : 6;
uint32_t reserved_6 : 1;
......@@ -386,7 +386,7 @@ union ctu_can_fd_btr_fd {
union ctu_can_fd_ewl_erp_fault_state {
uint32_t u32;
struct ctu_can_fd_ewl_erp_fault_state_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* EWL */
uint32_t ewl_limit : 8;
/* ERP */
......@@ -410,7 +410,7 @@ union ctu_can_fd_ewl_erp_fault_state {
union ctu_can_fd_rxc_txc {
uint32_t u32;
struct ctu_can_fd_rxc_txc_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* RXC */
uint32_t rxc_val : 16;
/* TXC */
......@@ -425,7 +425,7 @@ union ctu_can_fd_rxc_txc {
union ctu_can_fd_err_norm_err_fd {
uint32_t u32;
struct ctu_can_fd_err_norm_err_fd_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* ERR_NORM */
uint32_t err_norm_val : 16;
/* ERR_FD */
......@@ -440,7 +440,7 @@ union ctu_can_fd_err_norm_err_fd {
union ctu_can_fd_ctr_pres {
uint32_t u32;
struct ctu_can_fd_ctr_pres_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* CTR_PRES */
uint32_t ctpv : 9;
uint32_t ptx : 1;
......@@ -462,7 +462,7 @@ union ctu_can_fd_ctr_pres {
union ctu_can_fd_filter_a_mask {
uint32_t u32;
struct ctu_can_fd_filter_a_mask_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FILTER_A_MASK */
uint32_t bit_mask_a_val : 29;
uint32_t reserved_31_29 : 3;
......@@ -476,7 +476,7 @@ union ctu_can_fd_filter_a_mask {
union ctu_can_fd_filter_a_val {
uint32_t u32;
struct ctu_can_fd_filter_a_val_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FILTER_A_VAL */
uint32_t bit_val_a_val : 29;
uint32_t reserved_31_29 : 3;
......@@ -490,7 +490,7 @@ union ctu_can_fd_filter_a_val {
union ctu_can_fd_filter_b_mask {
uint32_t u32;
struct ctu_can_fd_filter_b_mask_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FILTER_B_MASK */
uint32_t bit_mask_b_val : 29;
uint32_t reserved_31_29 : 3;
......@@ -504,7 +504,7 @@ union ctu_can_fd_filter_b_mask {
union ctu_can_fd_filter_b_val {
uint32_t u32;
struct ctu_can_fd_filter_b_val_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FILTER_B_VAL */
uint32_t bit_val_b_val : 29;
uint32_t reserved_31_29 : 3;
......@@ -518,7 +518,7 @@ union ctu_can_fd_filter_b_val {
union ctu_can_fd_filter_c_mask {
uint32_t u32;
struct ctu_can_fd_filter_c_mask_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FILTER_C_MASK */
uint32_t bit_mask_c_val : 29;
uint32_t reserved_31_29 : 3;
......@@ -532,7 +532,7 @@ union ctu_can_fd_filter_c_mask {
union ctu_can_fd_filter_c_val {
uint32_t u32;
struct ctu_can_fd_filter_c_val_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FILTER_C_VAL */
uint32_t bit_val_c_val : 29;
uint32_t reserved_31_29 : 3;
......@@ -546,7 +546,7 @@ union ctu_can_fd_filter_c_val {
union ctu_can_fd_filter_ran_low {
uint32_t u32;
struct ctu_can_fd_filter_ran_low_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FILTER_RAN_LOW */
uint32_t bit_ran_low_val : 29;
uint32_t reserved_31_29 : 3;
......@@ -560,7 +560,7 @@ union ctu_can_fd_filter_ran_low {
union ctu_can_fd_filter_ran_high {
uint32_t u32;
struct ctu_can_fd_filter_ran_high_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FILTER_RAN_HIGH */
uint32_t bit_ran_high_val : 29;
uint32_t reserved_31_29 : 3;
......@@ -574,7 +574,7 @@ union ctu_can_fd_filter_ran_high {
union ctu_can_fd_filter_control_filter_status {
uint32_t u32;
struct ctu_can_fd_filter_control_filter_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FILTER_CONTROL */
uint32_t fanb : 1;
uint32_t fane : 1;
......@@ -627,7 +627,7 @@ union ctu_can_fd_filter_control_filter_status {
union ctu_can_fd_rx_mem_info {
uint32_t u32;
struct ctu_can_fd_rx_mem_info_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* RX_MEM_INFO */
uint32_t rx_buff_size : 13;
uint32_t reserved_15_13 : 3;
......@@ -645,7 +645,7 @@ union ctu_can_fd_rx_mem_info {
union ctu_can_fd_rx_pointers {
uint32_t u32;
struct ctu_can_fd_rx_pointers_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* RX_POINTERS */
uint32_t rx_wpp : 12;
uint32_t reserved_15_12 : 4;
......@@ -663,7 +663,7 @@ union ctu_can_fd_rx_pointers {
union ctu_can_fd_rx_status_rx_settings {
uint32_t u32;
struct ctu_can_fd_rx_status_rx_settings_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* RX_STATUS */
uint32_t rx_empty : 1;
uint32_t rx_full : 1;
......@@ -701,7 +701,7 @@ union ctu_can_fd_rx_data {
union ctu_can_fd_tx_status {
uint32_t u32;
struct ctu_can_fd_tx_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* TX_STATUS */
uint32_t tx1s : 4;
uint32_t tx2s : 4;
......@@ -731,7 +731,7 @@ enum ctu_can_fd_tx_status_tx1s {
union ctu_can_fd_tx_command {
uint32_t u32;
struct ctu_can_fd_tx_command_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* TX_COMMAND */
uint32_t txce : 1;
uint32_t txcr : 1;
......@@ -759,7 +759,7 @@ union ctu_can_fd_tx_command {
union ctu_can_fd_tx_priority {
uint32_t u32;
struct ctu_can_fd_tx_priority_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* TX_PRIORITY */
uint32_t txt1p : 3;
uint32_t reserved_3 : 1;
......@@ -785,7 +785,7 @@ union ctu_can_fd_tx_priority {
union ctu_can_fd_err_capt_alc {
uint32_t u32;
struct ctu_can_fd_err_capt_alc_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* ERR_CAPT */
uint32_t err_pos : 5;
uint32_t err_type : 3;
......@@ -825,7 +825,7 @@ enum ctu_can_fd_err_capt_err_type {
union ctu_can_fd_trv_delay {
uint32_t u32;
struct ctu_can_fd_trv_delay_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* TRV_DELAY */
uint32_t trv_delay_value : 16;
uint32_t reserved_31_16 : 16;
......@@ -855,7 +855,7 @@ union ctu_can_fd_tx_counter {
union ctu_can_fd_debug_register {
uint32_t u32;
struct ctu_can_fd_debug_register_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DEBUG_REGISTER */
uint32_t stuff_count : 3;
uint32_t destuff_count : 3;
......@@ -893,7 +893,7 @@ union ctu_can_fd_yolo_reg {
union ctu_can_fd_log_trig_config {
uint32_t u32;
struct ctu_can_fd_log_trig_config_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* LOG_TRIG_CONFIG */
uint32_t t_sof : 1;
uint32_t t_arbl : 1;
......@@ -941,7 +941,7 @@ union ctu_can_fd_log_trig_config {
union ctu_can_fd_log_capt_config {
uint32_t u32;
struct ctu_can_fd_log_capt_config_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* LOG_CAPT_CONFIG */
uint32_t c_sof : 1;
uint32_t c_arbl : 1;
......@@ -995,7 +995,7 @@ union ctu_can_fd_log_capt_config {
union ctu_can_fd_log_status_log_pointers {
uint32_t u32;
struct ctu_can_fd_log_status_log_pointers_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* LOG_STATUS */
uint32_t log_cfg : 1;
uint32_t log_rdy : 1;
......@@ -1022,7 +1022,7 @@ union ctu_can_fd_log_status_log_pointers {
union ctu_can_fd_log_command {
uint32_t u32;
struct ctu_can_fd_log_command_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* LOG_COMMAND */
uint32_t log_str : 1;
uint32_t log_abt : 1;
......@@ -1050,7 +1050,7 @@ union ctu_can_fd_log_capt_event_1 {
union ctu_can_fd_log_capt_event_2 {
uint32_t u32;
struct ctu_can_fd_log_capt_event_2_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* LOG_CAPT_EVENT_2 */
uint32_t evnt_type : 5;
uint32_t evnt_den : 3;
......
......@@ -7,8 +7,9 @@ python3.5 gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN
# To generate C header files (register map and frame format)
python3.5 gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName CAN_FD_frame_format
py gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName CAN_FD_frame_format
python3.5 gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName regs
python3.5 gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName frame
# To generate Lyx docu for register map
......
......@@ -97,6 +97,6 @@ if __name__ == '__main__':
write_license(lic_text, '*', of)
headerGen.prefix = "ctu_can_fd"
headerGen.create_addrMap_package("CTU_CAN_FD")
headerGen.create_addrMap_package(args.packName)
headerGen.commit_to_file()
\ No newline at end of file
headerGen.commit_to_file()
......@@ -144,7 +144,7 @@ class HeaderAddrGenerator(IpXactAddrGenerator):
self.headerGen.write_comment("This file is autogenerated, DO NOT EDIT!",
0, small=True)
self.headerGen.wr_nl()
self.headerGen.create_package(name)
self.headerGen.create_package((self.prefix + "_" + name).upper())
self.headerGen.wr_nl()
if (self.addrMap):
......@@ -165,4 +165,4 @@ class HeaderAddrGenerator(IpXactAddrGenerator):
def write_reg(self):
pass
\ No newline at end of file
pass
......@@ -214,9 +214,9 @@ class HeaderGenerator(LanBaseGenerator):
index = index + item.bitWidth
tmp.remove(tmp[-1])
# Write the bitfield values
# Write bitfield values
if (len(tmp) > 1):
self.__wr_line("#ifdef __BIG_ENDIAN_BITFIELD\n")
self.__wr_line("#ifdef __LITTLE_ENDIAN_BITFIELD\n")
for decl in sorted(tmp , key=lambda a: a.bitIndex):
self.write_decl(decl)
if (len(tmp) > 1):
......
......@@ -70,8 +70,8 @@ if __name__ == '__main__':
if (str_arg_to_bool(args.updHeader)):
print("Generating CAN FD memory registers Header file...\n")
os.system("""{} gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName CAN_FD_frame_format""".format(pythonAlias, args.xactSpec))
os.system("""{} gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName CAN_FD_frame_format""".format(pythonAlias, args.xactSpec))
os.system("""{} gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName regs""".format(pythonAlias, args.xactSpec))
os.system("""{} gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName frame""".format(pythonAlias, args.xactSpec))
print("\nDone\n")
if (str_arg_to_bool(args.updDocs)):
......
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