Commit 8bc20139 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '133-endian-fix' into 'master'

Resolve "Endian fix"

Closes #133

See merge request illeondr/CAN_FD_IP_Core!69
parents 98779f0c 5b8c52e9
......@@ -30,8 +30,8 @@
/* This file is autogenerated, DO NOT EDIT! */
#ifndef __CTU_CAN_FD__
#define __CTU_CAN_FD__
#ifndef __CTU_CAN_FD_FRAME__
#define __CTU_CAN_FD_FRAME__
/* Frame_format memory map */
enum ctu_can_fd_frame_format {
......@@ -49,7 +49,7 @@ enum ctu_can_fd_frame_format {
union ctu_can_fd_frame_form_w {
uint32_t u32;
struct ctu_can_fd_frame_form_w_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* FRAME_FORM_W */
uint32_t dlc : 4;
uint32_t reserved_4 : 1;
......@@ -109,7 +109,7 @@ enum ctu_can_fd_frame_form_w_esi_resvd {
union ctu_can_fd_identifier_w {
uint32_t u32;
struct ctu_can_fd_identifier_w_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* IDENTIFIER_W */
uint32_t identifier_ext : 18;
uint32_t identifier_base : 11;
......@@ -141,7 +141,7 @@ union ctu_can_fd_timestamp_u_w {
union ctu_can_fd_data_1_4_w {
uint32_t u32;
struct ctu_can_fd_data_1_4_w_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DATA_1_4_W */
uint32_t data_4 : 8;
uint32_t data_3 : 8;
......@@ -159,7 +159,7 @@ union ctu_can_fd_data_1_4_w {
union ctu_can_fd_data_5_8_w {
uint32_t u32;
struct ctu_can_fd_data_5_8_w_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DATA_5_8_W */
uint32_t data_8 : 8;
uint32_t data_7 : 8;
......@@ -177,7 +177,7 @@ union ctu_can_fd_data_5_8_w {
union ctu_can_fd_data_61_64_w {
uint32_t u32;
struct ctu_can_fd_data_61_64_w_s {
#ifdef __BIG_ENDIAN_BITFIELD
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DATA_61_64_W */
uint32_t data_64 : 8;
uint32_t data_63 : 8;
......
This diff is collapsed.
......@@ -7,8 +7,9 @@ python3.5 gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN
# To generate C header files (register map and frame format)
python3.5 gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName CAN_FD_frame_format
py gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName CAN_FD_frame_format
python3.5 gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName regs
python3.5 gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName frame
# To generate Lyx docu for register map
......
......@@ -97,6 +97,6 @@ if __name__ == '__main__':
write_license(lic_text, '*', of)
headerGen.prefix = "ctu_can_fd"
headerGen.create_addrMap_package("CTU_CAN_FD")
headerGen.create_addrMap_package(args.packName)
headerGen.commit_to_file()
\ No newline at end of file
headerGen.commit_to_file()
......@@ -144,7 +144,7 @@ class HeaderAddrGenerator(IpXactAddrGenerator):
self.headerGen.write_comment("This file is autogenerated, DO NOT EDIT!",
0, small=True)
self.headerGen.wr_nl()
self.headerGen.create_package(name)
self.headerGen.create_package((self.prefix + "_" + name).upper())
self.headerGen.wr_nl()
if (self.addrMap):
......@@ -165,4 +165,4 @@ class HeaderAddrGenerator(IpXactAddrGenerator):
def write_reg(self):
pass
\ No newline at end of file
pass
......@@ -214,9 +214,9 @@ class HeaderGenerator(LanBaseGenerator):
index = index + item.bitWidth
tmp.remove(tmp[-1])
# Write the bitfield values
# Write bitfield values
if (len(tmp) > 1):
self.__wr_line("#ifdef __BIG_ENDIAN_BITFIELD\n")
self.__wr_line("#ifdef __LITTLE_ENDIAN_BITFIELD\n")
for decl in sorted(tmp , key=lambda a: a.bitIndex):
self.write_decl(decl)
if (len(tmp) > 1):
......
......@@ -70,8 +70,8 @@ if __name__ == '__main__':
if (str_arg_to_bool(args.updHeader)):
print("Generating CAN FD memory registers Header file...\n")
os.system("""{} gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName CAN_FD_frame_format""".format(pythonAlias, args.xactSpec))
os.system("""{} gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName CAN_FD_frame_format""".format(pythonAlias, args.xactSpec))
os.system("""{} gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Regs --fieldMap Regs --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName regs""".format(pythonAlias, args.xactSpec))
os.system("""{} gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec {} --addrMap Frame_format --fieldMap Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName frame""".format(pythonAlias, args.xactSpec))
print("\nDone\n")
if (str_arg_to_bool(args.updDocs)):
......
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