Commit 8a4722fd authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Prescaler new implementation.

parent acc97185
......@@ -436,6 +436,12 @@ architecture rtl of CAN_top_level is
signal sync_nbt_del_1 : std_logic;
signal sync_dbt_del_1 : std_logic;
-- Trigger outputs from Prescaler
signal sample_nbt_i : std_logic_vector(2 downto 0);
signal sample_dbt_i : std_logic_vector(2 downto 0);
signal sync_nbt_i : std_logic_vector(1 downto 0);
signal sync_dbt_i : std_logic_vector(1 downto 0);
signal sp_control : std_logic_vector(1 downto 0);
signal sync_control : std_logic_vector(1 downto 0);
......@@ -777,6 +783,28 @@ begin
);
prescaler_comp : prescaler
generic map(
reset_polarity => '0',
capt_btr => false,
capt_tseg_1 => true,
capt_tseg_2 => false,
capt_sjw => false,
-- Width of Bit time segments
tseg1_nbt_width => 8,
tseg2_nbt_width => 6,
tq_nbt_width => 8,
sjw_nbt_width => 5,
tseg1_dbt_width => 7,
tseg2_dbt_width => 5,
tq_dbt_width => 8,
sjw_dbt_width => 5,
ipt_length => 4,
sync_trigger_count => 2,
sample_trigger_count => 3
)
port map(
clk_sys => clk_sys,
res_n => res_n_int,
......@@ -785,22 +813,30 @@ begin
drv_bus => drv_bus,
clk_tq_nbt => clk_tq_nbt,
clk_tq_dbt => clk_tq_dbt,
sample_nbt => sample_nbt,
sample_dbt => sample_dbt,
sample_nbt => sample_nbt_i,
sample_dbt => sample_dbt_i,
bt_FSM_out => bt_FSM_out,
sample_nbt_del_1 => sample_nbt_del_1,
sample_dbt_del_1 => sample_dbt_del_1,
sample_nbt_del_2 => sample_nbt_del_2,
sample_dbt_del_2 => sample_dbt_del_2,
sync_nbt => sync_nbt,
sync_dbt => sync_dbt,
sync_nbt_del_1 => sync_nbt_del_1,
sync_dbt_del_1 => sync_dbt_del_1,
sync_nbt => sync_nbt_i,
sync_dbt => sync_dbt_i,
data_tx => data_tx,
hard_sync_edge_valid => hard_sync_edge_valid,
sp_control => sp_control,
sync_control => sync_control
);
-- Temporary internal connections. Will be replaced during protocol
-- control re-work!
sample_nbt <= sample_nbt_i(2);
sample_dbt <= sample_dbt_i(2);
sample_nbt_del_1 <= sample_nbt_i(1);
sample_dbt_del_1 <= sample_dbt_i(1);
sample_nbt_del_2 <= sample_dbt_i(0);
sample_dbt_del_2 <= sample_dbt_i(0);
sync_nbt_del_1 <= sync_nbt_i(0);
sync_dbt_del_1 <= sync_dbt_i(0);
sync_nbt <= sync_nbt_i(1);
sync_dbt <= sync_dbt_i(1);
bus_sampling_comp : bus_sampling
generic map (
......
......@@ -509,10 +509,8 @@ begin
if (i = 17) then
case bt_FSM is
when sync => bit_type_vect <= "0001";
when prop => bit_type_vect <= "0010";
when ph1 => bit_type_vect <= "0100";
when ph2 => bit_type_vect <= "1000";
when tseg1 => bit_type_vect <= "0001";
when tseg2 => bit_type_vect <= "1000";
when others => bit_type_vect <= "0000";
end case;
end if;
......
......@@ -697,6 +697,24 @@ package can_components is
-- Prescaler module
----------------------------------------------------------------------------
component prescaler is
generic(
reset_polarity : std_logic := '0';
capt_btr : boolean := false;
capt_tseg_1 : boolean := true;
capt_tseg_2 : boolean := false;
capt_sjw : boolean := false;
tseg1_nbt_width : natural := 8;
tseg2_nbt_width : natural := 6;
tq_nbt_width : natural := 8;
sjw_nbt_width : natural := 5;
tseg1_dbt_width : natural := 7;
tseg2_dbt_width : natural := 5;
tq_dbt_width : natural := 8;
sjw_dbt_width : natural := 5;
ipt_length : natural := 4;
sync_trigger_count : natural range 2 to 8 := 2;
sample_trigger_count : natural range 2 to 8 := 3
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
......@@ -705,16 +723,10 @@ package can_components is
signal drv_bus : in std_logic_vector(1023 downto 0);
signal clk_tq_nbt : out std_logic;
signal clk_tq_dbt : out std_logic;
signal sample_nbt : out std_logic;
signal sample_dbt : out std_logic;
signal sample_nbt_del_1 : out std_logic;
signal sample_dbt_del_1 : out std_logic;
signal sample_nbt_del_2 : out std_logic;
signal sample_dbt_del_2 : out std_logic;
signal sync_nbt : out std_logic;
signal sync_dbt : out std_logic;
signal sync_nbt_del_1 : out std_logic;
signal sync_dbt_del_1 : out std_logic;
signal sample_nbt : out std_logic_vector(sample_trigger_count - 1 downto 0);
signal sample_dbt : out std_logic_vector(sample_trigger_count - 1 downto 0);
signal sync_nbt : out std_logic_vector(sync_trigger_count - 1 downto 0);
signal sync_dbt : out std_logic_vector(sync_trigger_count - 1 downto 0);
signal bt_FSM_out : out bit_time_type;
signal data_tx : in std_logic;
signal hard_sync_edge_valid : out std_logic;
......@@ -723,6 +735,166 @@ package can_components is
);
end component;
component bit_time_cfg_capture is
generic (
reset_polarity : std_logic := '0';
capt_btr : boolean := false;
capt_tseg_1 : boolean := true;
capt_tseg_2 : boolean := false;
capt_sjw : boolean := false;
tseg1_nbt_width : natural := 8;
tseg2_nbt_width : natural := 8;
tq_nbt_width : natural := 8;
sjw_nbt_width : natural := 5;
tseg1_dbt_width : natural := 8;
tseg2_dbt_width : natural := 8;
tq_dbt_width : natural := 8;
sjw_dbt_width : natural := 5
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal drv_bus : in std_logic_vector(1023 downto 0);
signal tseg1_nbt : out std_logic_vector(tseg1_nbt_width - 1 downto 0);
signal tseg2_nbt : out std_logic_vector(tseg2_nbt_width - 1 downto 0);
signal brp_nbt : out std_logic_vector(tq_nbt_width - 1 downto 0);
signal sjw_nbt : out std_logic_vector(sjw_nbt_width - 1 downto 0);
signal tseg1_dbt : out std_logic_vector(tseg1_dbt_width - 1 downto 0);
signal tseg2_dbt : out std_logic_vector(tseg2_dbt_width - 1 downto 0);
signal brp_dbt : out std_logic_vector(tq_dbt_width - 1 downto 0);
signal sjw_dbt : out std_logic_vector(sjw_dbt_width - 1 downto 0)
);
end component;
component ipt_checker is
generic (
reset_polarity : std_logic := '0';
ipt_length : natural := 4
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal ipt_req : in std_logic;
signal ipt_gnt : out std_logic
);
end component;
component resynchronisation is
generic (
reset_polarity : std_logic := '0';
sjw_width : natural := 4;
tseg1_width : natural := 8;
tseg2_width : natural := 8;
bt_width : natural := 8
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal resync_edge_valid : in std_logic;
signal ipt_ok : in std_logic;
signal is_tseg1 : in std_logic;
signal is_tseg2 : in std_logic;
signal tseg_1 : in std_logic_vector(tseg1_width - 1 downto 0);
signal tseg_2 : in std_logic_vector(tseg2_width - 1 downto 0);
signal sjw : in std_logic_vector(sjw_width - 1 downto 0);
signal bt_counter : in std_logic_vector(bt_width - 1 downto 0);
signal segm_end : in std_logic;
signal h_sync_valid : in std_logic;
signal exit_segm_req : out std_logic
);
end component;
component bit_time_counters is
generic (
reset_polarity : std_logic := '0';
bt_width : natural := 8;
tq_width : natural := 8
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal prescaler : in std_logic_vector(tq_width - 1 downto 0);
signal tq_reset : in std_logic;
signal bt_reset : in std_logic;
signal tq_edge : out std_logic;
signal bt_counter : out std_logic_vector(bt_width - 1 downto 0)
);
end component;
component segment_end_detector is
generic (
reset_polarity : std_logic := '0'
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal sp_control : in std_logic_vector(1 downto 0);
signal h_sync_edge_valid : in std_logic;
signal exit_segm_req_nbt : in std_logic;
signal exit_segm_req_dbt : in std_logic;
signal ipt_ok : in std_logic;
signal is_tseg1 : in std_logic;
signal is_tseg2 : in std_logic;
signal tq_edge_nbt : in std_logic;
signal tq_edge_dbt : in std_logic;
signal segm_end : out std_logic;
signal h_sync_valid : out std_logic
);
end component;
component bit_time_fsm is
generic (
reset_polarity : std_logic := '0'
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal segm_end : in std_logic;
signal h_sync_valid : in std_logic;
signal drv_ena : in std_logic;
signal is_tseg1 : out std_logic;
signal is_tseg2 : out std_logic;
signal sample_req : out std_logic;
signal sync_req : out std_logic
);
end component;
component synchronisation_checker is
generic (
reset_polarity : std_logic := '0'
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal sync_control : in std_logic_vector(1 downto 0);
signal sync_edge : in std_logic;
signal no_pos_resync : in std_logic;
signal segment_end : out std_logic;
signal is_tseg1 : in std_logic;
signal is_tseg2 : in std_logic;
signal resync_edge_valid : out std_logic;
signal h_sync_edge_valid : out std_logic
);
end component;
component trigger_generator is
generic (
reset_polarity : std_logic := '0';
sync_trigger_count : natural range 2 to 8 := 2;
sample_trigger_count : natural range 2 to 8 := 3
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal sample_req : in std_logic;
signal sync_req : in std_logic;
signal sp_control : in std_logic_vector(1 downto 0);
signal sample_nbt : out std_logic_vector(sample_trigger_count - 1 downto 0);
signal sample_dbt : out std_logic_vector(sample_trigger_count - 1 downto 0);
signal sync_nbt : out std_logic_vector(sync_trigger_count - 1 downto 0);
signal sync_dbt : out std_logic_vector(sync_trigger_count - 1 downto 0)
);
end component;
----------------------------------------------------------------------------
-- Bus Sampling module
......
......@@ -123,11 +123,8 @@ package can_types is
);
type bit_time_type is (
sync,
prop,
ph1,
ph2,
h_sync,
tseg1,
tseg2,
reset
);
......
This diff is collapsed.
......@@ -41,16 +41,18 @@
--------------------------------------------------------------------------------
-- Purpose:
-- Information processing Time checker.
-- Contains two counters:
-- 1. Time Quanta counter.
-- 2. Bit time counter.
--
-- Checks length of Information processing time after Sample point between
-- PH1 and PH2. Functions like a half-handshake. When 'ipt_req' comes, interna
-- shift register is preloaded. This shift register shifts each clock cycle
-- and after input value was shifted till the very end, 'ipt_gnt' is set
-- high and remains high till the next 'ipt_req'.
---------------------------------------------------------------------------------------------------------------------------------------------
-- Time Quanta counter counts duration of Time quanta segment and provides
--- Time Quanta edge signal.
-- Bit Time counter counts with granularity of Time Quanta and provides value
-- of Bit Time counter to the output.
--
--------------------------------------------------------------------------------
-- Revision History:
-- 03.02.2019 Created file
-- 15.02.2019 Created file
--------------------------------------------------------------------------------
Library ieee;
......@@ -71,13 +73,16 @@ use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
entity ipt_checker is
entity bit_time_counters is
generic (
-- Reset polarity
reset_polarity : std_logic := '0';
-- Length of Information processing time in clock cycles.
ipt_length : natural := 4
reset_polarity : std_logic := '0';
-- Bit Time counter width
bt_width : natural := 8;
-- Time Qunata counter width
tq_width : natural := 8
);
port(
-----------------------------------------------------------------------
......@@ -87,86 +92,117 @@ entity ipt_checker is
signal res_n : in std_logic;
-----------------------------------------------------------------------
-- Control interface (Handshake-like)
-- Control signals
-----------------------------------------------------------------------
-- Prescaler value
signal prescaler : in std_logic_vector(tq_width - 1 downto 0);
-- Time Quanta reset (synchronous)
signal tq_reset : in std_logic;
-- Bit Time reset (synchronous)
signal bt_reset : in std_logic;
-----------------------------------------------------------------------
-- Status signals
-----------------------------------------------------------------------
signal ipt_req : in std_logic;
signal ipt_gnt : out std_logic
-- Time Quanta edge
signal tq_edge : out std_logic;
-- Bit Time counter
signal bt_counter : out std_logic_vector(bt_width - 1 downto 0)
);
end entity;
architecture rtl of bit_time_counters is
-- Time Quanta Counter
signal tq_counter_d : std_logic_vector(tq_width - 1 downto 0);
signal tq_counter_q : std_logic_vector(tq_width - 1 downto 0);
signal tq_counter_ce : std_logic;
architecture rtl of ipt_checker is
-- Internal Shift register
signal ipt_sr : std_logic_vector(ipt_length - 1 downto 0);
signal ipt_sr_nxt : std_logic_vector(ipt_length - 1 downto 0);
signal tq_edge_i : std_logic;
-- Clock enable for internal shift register.
signal ipt_sr_ce : std_logic;
constant tq_zeroes : std_logic_vector(tq_width - 1 downto 0) :=
(OTHERS => '0');
constant tq_run_th : std_logic_vector(tq_width - 1 downto 0) :=
(0 => '1', OTHERS => '0');
-- IPT shift register is empty
signal ipt_empty : std_logic;
-- Bit Time counter
signal bt_counter_d : std_logic_vector(bt_width - 1 downto 0);
signal bt_counter_q : std_logic_vector(bt_width - 1 downto 0);
---------------------------------------------------------------------------
-- IPT constants
---------------------------------------------------------------------------
constant IPT_ZEROES : std_logic_vector(ipt_length - 1 downto 0) :=
constant bt_zeroes : std_logic_vector(bt_width - 1 downto 0) :=
(OTHERS => '0');
constant IPT_ONES : std_logic_vector(ipt_length - 1 downto 0) :=
constant bt_ones : std_logic_vector(bt_width - 1 downto 0) :=
(OTHERS => '1');
begin
begin
---------------------------------------------------------------------------
-- Shift register clock enable. Tick when:
-- 1. There is a request to measure IPT till grant (shift reg preload)
-- 2. Shift register is not empty, shifting is in progress.
-- If prescaler is defined as 0 or 1, there is no need to run the counter!
-- Run it only when Prescaler is higher than 1!
---------------------------------------------------------------------------
ipt_sr_ce <= '1' when (ipt_req = '1') else
'1' when (ipt_empty = '0') else
'0';
tq_counter_ce <= '1' when (prescaler > tq_run_th) else
'0';
-- Is shift register empty??
ipt_empty <= '1' when (ipt_sr = IPT_ZEROES) else
'0';
---------------------------------------------------------------------------
-- IPT Shift register. Next value:
-- 1. Preload upon request
-- 2. Shift to the right
-- Time quanta counter next value:
-- 1. Erase when reaching value of prescaler.
-- 2. Erase when re-started.
-- 3. Add 1 ohterwise!
---------------------------------------------------------------------------
ipt_sr_nxt <= IPT_ONES when (ipt_req = '1') else
'0' & ipt_sr(ipt_length - 1 downto 1);
tq_counter_d <=
(OTHERS => '0') when (unsigned(tq_counter_q) = unsigned(prescaler) - 1)
else
(OTHERS => '0') when (tq_reset = '1')
else
std_logic_vector(unsigned(tq_counter_q) + 1);
tq_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
tq_counter_q <= (OTHERS => '0');
elsif (rising_edge(clk_sys)) then
if (tq_counter_ce = '1') then
tq_counter_q <= tq_counter_d;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- IPT Shift register. Register assignment
-- Time quanta edge
---------------------------------------------------------------------------
ipt_sr_proc : process(res_n, clk_sys)
tq_edge_i <= '1' when (tq_counter_ce = '0' or tq_counter_q = tq_zeroes) else
'0';
tq_edge <= tq_edge_i;
---------------------------------------------------------------------------
-- Bit time counter
---------------------------------------------------------------------------
bt_counter_d <= bt_zeroes when (bt_reset = '1') else
std_logic_vector(unsigned(bt_counter_q) + 1);
bt_counter_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
ipt_sr <= IPT_ZEROES;
bt_counter_q <= (OTHERS => '0');
elsif (rising_edge(clk_sys)) then
if (ipt_sr_ce = '1') then
ipt_sr <= ip_sr_nxt;
if (tq_edge_i = '1') then
bt_counter_q <= bt_counter_d;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Grant computation. We grant only if the shift register has shifted
-- till the very end!
---------------------------------------------------------------------------
ipt_gnt <= '1' when (ipt_empty = '1' and ipt_req = '0') else
'0';
-- Assertions
---------------------------------------------------------------------------
-- Check that no next IPT request will come till grant to the first
-- request has been given. This should not occur since there should not
-- be sample points so close to each other.
---------------------------------------------------------------------------
-- psl ipt_half_handshake_asrt :
-- assert (not (ipt_empty = '0' and ipt_req = '1'));
-- psl default clock is rising_edge(clk_sys);
--
-- psl no_bt_overflow_asrt : assert never
-- (bt_counter_q = bt_ones and tq_edge = '1' and bt_reset = '0');
end architecture rtl;
\ No newline at end of file
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Bit time FSM.
--------------------------------------------------------------------------------
-- Revision History:
-- 15.02.2019 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
use work.can_constants.all;
use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
entity bit_time_fsm is
generic (
-- Reset polarity
reset_polarity : std_logic := '0'
);
port(
-----------------------------------------------------------------------
-- Clock and reset
-----------------------------------------------------------------------
signal clk_sys : in std_logic;
signal res_n : in std_logic;
-----------------------------------------------------------------------
-- Control interface
-----------------------------------------------------------------------
-- Signalling segment end (either due to re-sync, or reaching expected
-- length of segment)
signal segm_end : in std_logic;
signal h_sync_valid : in std_logic;
-- Core is enabled
signal drv_ena : in std_logic;
-----------------------------------------------------------------------
-- Status signals