Commit 87743d32 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch...

Merge branch '381-dff-entity-name-seems-to-conflict-with-quartus-prime-reserved-primitve-name' into 'master'

Resolve "dff entity name seems to conflict with Quartus Prime reserved primitve name"

Closes #381

See merge request !367
parents fa11348a 9082a56f
Pipeline #24976 passed with stage
in 1 minute and 32 seconds
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Module:
-- Single Flip-flop (without reset).
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
-- Clock
clk : in std_logic;
-- Data input (D)
input : in std_logic;
-- Data output (Q)
output : out std_logic
);
end dff;
architecture rtl of dff is
begin
-- DFF process
dff_proc : process (clk)
begin
if (rising_edge(clk)) then
output <= input;
end if;
end process;
end rtl;
\ No newline at end of file
......@@ -677,12 +677,6 @@
<spirit:logicalName>ctu_can_fd_rtl</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>common/dff.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>ctu_can_fd_rtl</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>common/dff_arst.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -1227,13 +1221,6 @@
<spirit:logicalName>ctu_can_fd_rtl</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>common/dff.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>ctu_can_fd_rtl</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>common/dff_arst.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......
......@@ -101,18 +101,6 @@ package cmn_lib is
);
end component dff_arst;
component dff is
port (
-- Clock
clk : in std_logic;
-- Data input (D)
input : in std_logic;
-- Data output (Q)
output : out std_logic
);
end component dff;
component dlc_decoder is
port (
......
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