Commit 8675be17 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '351-resolve-synthesis-warnings' into 'master'

src: Resolve warnings from Vivado synthesis.

Closes #351

See merge request !333
parents e8bf93bf 42f4d37d
Pipeline #18730 passed with stage
in 17 seconds
Subproject commit 58c058cc9103b259a10a50406454fe978171f646
Subproject commit db08f2681854aa081210b26c4499d97d42c1c346
......@@ -519,7 +519,6 @@ begin
-- Operation control FSM Interface
is_transmitter => is_transmitter, -- IN
is_receiver => is_receiver, -- IN
is_idle => is_idle, -- IN
arbitration_lost => arbitration_lost_i, -- OUT
set_transmitter => set_transmitter, -- OUT
set_receiver => set_receiver, -- OUT
......@@ -702,7 +701,6 @@ begin
crc_enable => crc_enable, -- IN
crc_spec_enable => crc_spec_enable, -- IN
crc_calc_from_rx => crc_calc_from_rx, -- IN
is_receiver => is_receiver, -- IN
load_init_vect => load_init_vect, -- IN
-- CRC Outputs
......
......@@ -146,9 +146,6 @@ entity can_crc is
-- Use RX Data for CRC calculation
crc_calc_from_rx :in std_logic;
-- Unit is receiver of a frame
is_receiver :in std_logic;
-- Load CRC Initialization vector
load_init_vect :in std_logic;
......
......@@ -173,7 +173,6 @@ architecture rtl of fault_confinement is
signal drv_erp : std_logic_vector(8 downto 0);
signal drv_ctr_val : std_logic_vector(8 downto 0);
signal drv_ctr_sel : std_logic_vector(3 downto 0);
signal drv_clr_err_ctrs : std_logic;
signal drv_ena : std_logic;
-- Internal TX/RX Error counter values
......@@ -196,7 +195,6 @@ begin
drv_erp <= '0' & drv_bus(DRV_ERP_HIGH downto DRV_ERP_LOW);
drv_ctr_val <= drv_bus(DRV_CTR_VAL_HIGH downto DRV_CTR_VAL_LOW);
drv_ctr_sel <= drv_bus(DRV_CTR_SEL_HIGH downto DRV_CTR_SEL_LOW);
drv_clr_err_ctrs <= drv_bus(DRV_ERR_CTR_CLR);
drv_ena <= drv_bus(DRV_ENA_INDEX);
dff_arst_inst : dff_arst
......
......@@ -231,9 +231,6 @@ entity protocol_control is
-- Unit is receiver
is_receiver :in std_logic;
-- Unit is idle
is_idle :in std_logic;
-- Loss of arbitration -> Turn receiver!
arbitration_lost :out std_logic;
......@@ -635,15 +632,13 @@ begin
---------------------------------------------------------------------------
endian_swapper_tx_inst : endian_swapper
generic map(
G_SWAP_BY_SIGNAL => false,
G_SWAP_GEN => true,
G_WORD_SIZE => 4, -- Number of Groups
G_GROUP_SIZE => 8 -- Group size (bits)
)
port map(
input => tran_word, -- IN
output => tran_word_swapped, -- OUT
swap_in => '0' -- IN
output => tran_word_swapped -- OUT
);
......@@ -780,7 +775,6 @@ begin
-- Operation control interface
is_transmitter => is_transmitter, -- IN
is_receiver => is_receiver, -- IN
is_idle => is_idle, -- IN
arbitration_lost => arbitration_lost_i, -- OUT
set_transmitter => set_transmitter, -- OUT
set_receiver => set_receiver, -- OUT
......@@ -976,7 +970,6 @@ begin
err_frm_req => err_frm_req, -- IN
is_err_active => is_err_active, -- IN
bst_ctr => bst_ctr, -- IN
tran_word => tran_word, -- IN
tran_identifier => tran_identifier, -- IN
tran_word_swapped => tran_word_swapped, -- IN
tran_dlc => tran_dlc -- IN
......
......@@ -427,9 +427,6 @@ entity protocol_control_fsm is
-- Unit is receiver
is_receiver :in std_logic;
-- Unit is idle
is_idle :in std_logic;
-- Loss of arbitration -> Turn receiver!
arbitration_lost :out std_logic;
......@@ -1306,8 +1303,8 @@ begin
is_receiver, crc_match, drv_ack_forb, drv_self_test_ena, tx_frame_ready,
go_to_suspend, frame_start, ctrl_ctr_one, drv_bus_off_reset_q,
reinteg_ctr_expired, first_err_delim_q, go_to_stuff_count,
crc_length_i, data_length_bits_c, ctrl_ctr_mem_index, is_bus_off
)
crc_length_i, data_length_bits_c, ctrl_ctr_mem_index, is_bus_off,
block_txtb_unlock)
begin
-----------------------------------------------------------------------
......
......@@ -156,9 +156,6 @@ entity tx_shift_reg is
-----------------------------------------------------------------------
-- TXT Buffers interface
-----------------------------------------------------------------------
-- TXT Buffer RAM word
tran_word :in std_logic_vector(31 downto 0);
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
......
......@@ -674,7 +674,6 @@ begin
txtb_ptr => txtb_ptr, -- IN
-- Memory registers interface
drv_bus => drv_bus, -- IN
txtb_prorities => txtb_prorities, -- IN
timestamp => timestamp -- IN
);
......
......@@ -68,11 +68,7 @@ use work.CAN_FD_frame_format.all;
entity endian_swapper is
generic (
-- If true, "swap_in" signal selects between swapping/non-swapping.
-- If false "swap_gen" generic selects bewtween swapping/non-swapping.
G_SWAP_BY_SIGNAL : boolean := false;
-- When true, output word is endian swapped as long as "swap_by_signal"
-- is true. Otherwise it has no meaning.
G_SWAP_GEN : boolean := false;
......@@ -88,11 +84,7 @@ entity endian_swapper is
input : in std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0);
-- Data output
output : out std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0);
-- Swap signal (used only when "swap_by_signal=true")
-- Swaps endian when '1', keeps otherwise.
swap_in : in std_logic
output : out std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0)
);
end entity;
......@@ -123,30 +115,19 @@ begin
input(u_ind_orig downto l_ind_orig);
end loop;
end process;
---------------------------------------------------------------------------
-- Swapping by generic
---------------------------------------------------------------------------
swap_by_generic_gen : if (not G_SWAP_BY_SIGNAL) generate
-- Swap
swap_by_generic_true_gen : if (G_SWAP_GEN) generate
output <= swapped;
end generate swap_by_generic_true_gen;
-- Don't Swap
swap_by_generic_false_gen : if (not G_SWAP_GEN) generate
output <= input;
end generate swap_by_generic_false_gen;
end generate swap_by_generic_gen;
-- Swap
swap_by_generic_true_gen : if (G_SWAP_GEN) generate
output <= swapped;
end generate swap_by_generic_true_gen;
---------------------------------------------------------------------------
-- Swapping by input
---------------------------------------------------------------------------
swap_by_input_gen : if (G_SWAP_BY_SIGNAL) generate
output <= swapped when (swap_in = '1') else
input;
end generate swap_by_input_gen;
-- Don't Swap
swap_by_generic_false_gen : if (not G_SWAP_GEN) generate
output <= input;
end generate swap_by_generic_false_gen;
end architecture;
......@@ -69,9 +69,6 @@ entity inf_ram_wrapper is
-- Address width (in bits)
G_ADDRESS_WIDTH : natural := 8;
-- RAM content reset upon reset
G_SIMULATION_RESET : boolean := true;
-- Synchronous read
G_SYNC_READ : boolean := true
);
......@@ -123,21 +120,10 @@ begin
----------------------------------------------------------------------------
ram_write_process : process(res_n, clk_sys)
begin
if (res_n = G_RESET_POLARITY) then
-- pragma translate_off
if (G_SIMULATION_RESET) then
ram_memory <= (OTHERS => (OTHERS => '0'));
end if;
-- pragma translate_on
elsif (rising_edge(clk_sys)) then
-- Store the data into the RAM memory
if (rising_edge(clk_sys)) then
if (write = '1') then
ram_memory(to_integer(unsigned(addr_A))) <= data_in;
end if;
end if;
end process;
......@@ -151,17 +137,10 @@ begin
sync_read_gen : if (G_SYNC_READ) generate
ram_read_process : process(res_n, clk_sys)
begin
if (res_n = G_RESET_POLARITY) then
-- pragma translate_off
if (G_SIMULATION_RESET) then
data_out <= (OTHERS => '0');
end if;
-- pragma translate_on
if (res_n = G_RESET_POLARITY) then
data_out <= (OTHERS => '0');
elsif (rising_edge(clk_sys)) then
data_out <= int_read_data;
end if;
end process;
end generate;
......
......@@ -792,9 +792,6 @@ package can_components is
-- Use RX Data for CRC calculation
crc_calc_from_rx :in std_logic;
-- Unit is receiver of a frame
is_receiver :in std_logic;
-- Load CRC Initialization vector
load_init_vect :in std_logic;
......@@ -1809,9 +1806,6 @@ package can_components is
-- Unit is receiver
is_receiver :in std_logic;
-- Unit is idle
is_idle :in std_logic;
-- Loss of arbitration -> Turn receiver!
arbitration_lost :out std_logic;
......@@ -2076,9 +2070,6 @@ package can_components is
-- Unit is receiver
is_receiver :in std_logic;
-- Unit is idle
is_idle :in std_logic;
-- Loss of arbitration -> Turn receiver!
arbitration_lost :out std_logic;
......@@ -2546,9 +2537,6 @@ package can_components is
-----------------------------------------------------------------------
-- TXT Buffers interface
-----------------------------------------------------------------------
-- TXT Buffer RAM word
tran_word :in std_logic_vector(31 downto 0);
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
......@@ -3354,9 +3342,6 @@ package can_components is
-----------------------------------------------------------------------
-- Segment end (either due to re-sync, or reaching expected length)
segm_end : in std_logic;
-- Hard synchronisation is valid
h_sync_valid : in std_logic;
-- CTU CAN FD is enabled
drv_ena : in std_logic;
......@@ -3690,9 +3675,6 @@ package can_components is
-- Sync Trigger Request (TX Trigger request)
tx_trig_req : in std_logic;
-- Sample control (Nominal, Data, Secondary)
sp_control : in std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- Trigger outputs
-----------------------------------------------------------------------
......@@ -3734,9 +3716,6 @@ package can_components is
-- Abort storing of RX Frame to RX Buffer.
rec_abort_f :in std_logic;
-- Start of Frame pulse
sof_pulse :in std_logic;
-----------------------------------------------------------------------
-- FSM outputs
-----------------------------------------------------------------------
......@@ -3810,12 +3789,6 @@ package can_components is
-- RX Buffer RAM is being read by SW
read_increment :in std_logic;
-----------------------------------------------------------------------
-- Memory registers interface
-----------------------------------------------------------------------
-- Driving bus
drv_bus :in std_logic_vector(1023 downto 0);
-----------------------------------------------------------------------
-- Status outputs
-----------------------------------------------------------------------
......@@ -4174,9 +4147,6 @@ package can_components is
-----------------------------------------------------------------------
-- Memory registers interface
-----------------------------------------------------------------------
-- Driving Bus
drv_bus :in std_logic_vector(1023 downto 0);
-- Priorities of TXT Buffers
txtb_prorities :in t_txt_bufs_priorities;
......@@ -4369,9 +4339,6 @@ package can_components is
-- Address width (in bits)
G_ADDRESS_WIDTH : natural := 8;
-- RAM content reset upon reset
G_SIMULATION_RESET : boolean := true;
-- Synchronous read
G_SYNC_READ : boolean := true
);
......
......@@ -133,10 +133,6 @@ package cmn_lib is
component endian_swapper is
generic (
-- If true, "swap_in" signal selects between swapping/non-swapping.
-- If false "swap_gen" generic selects bewtween swapping/non-swapping.
G_SWAP_BY_SIGNAL : boolean := false;
-- When true, output word is endian swapped as long as "swap_by_signal"
-- is true. Otherwise it has no meaning.
G_SWAP_GEN : boolean := false;
......@@ -152,11 +148,7 @@ package cmn_lib is
input : in std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0);
-- Data output
output : out std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0);
-- Swap signal (used only when "swap_by_signal=true")
-- Swaps endian when '1', keeps otherwise.
swap_in : in std_logic
output : out std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0)
);
end component;
......@@ -174,9 +166,6 @@ package cmn_lib is
-- Address width (in bits)
G_ADDRESS_WIDTH : natural := 8;
-- RAM content reset upon reset
G_SIMULATION_RESET : boolean := true;
-- Synchronous read
G_SYNC_READ : boolean := true
);
......
......@@ -94,16 +94,21 @@ end entity memory_reg;
architecture rtl of memory_reg is
pure function bit_in_mask(mask_vec: std_logic_vector; bit_pos : natural)
return std_ulogic is
begin
if mask_vec'ascending then
return mask_vec(mask_vec'length - 1 - bit_pos);
else
return mask_vec(bit_pos);
end if;
--return mask_vec(bit_pos);
end function bit_in_mask;
---------------------------------------------------------------------------
-- Create new constants for reset value, implemented etc.
-- This is important because generic can't be directly passed to if-generate
-- condition. In instance of the module, generic is filled like so:
-- data_mask => "0000000110011111"
-- Some tools interpret this vector as 'downto' (GHDL), other tools as 'to'.
-- (Vivado). We want to keep the module generic therefore we will not give
-- range (and direction) to generic "data_mask", but we must tell the tool
-- how to interpret this constant that is passed without "to/downto"!
-- So we re-declare constants internally and give direction to them.
-- Tool should assign the constant the same way as it was passed.
---------------------------------------------------------------------------
constant data_mask_i : std_logic_vector(data_width - 1 downto 0) := data_mask;
constant reset_value_i : std_logic_vector(data_width - 1 downto 0) := reset_value;
constant auto_clear_i : std_logic_vector(data_width - 1 downto 0) := auto_clear;
-- Register implementation itself!
signal reg_value_r : std_logic_vector(data_width - 1 downto 0);
......@@ -150,17 +155,17 @@ begin
------------------------------------------------------------------------
-- Register implementation itself
------------------------------------------------------------------------
reg_present_gen : if (bit_in_mask(data_mask, i) = '1') generate
reg_present_gen : if (data_mask_i(i) = '1') generate
--------------------------------------------------------------------
-- Regular register (DFF)
--------------------------------------------------------------------
reg_regular_gen : if (bit_in_mask(auto_clear, i) = '0') generate
reg_regular_gen : if (auto_clear_i(i) = '0') generate
reg_access_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
reg_value_r(i) <= bit_in_mask(reset_value, i);
reg_value_r(i) <= reset_value_i(i);
elsif (rising_edge(clk_sys)) then
if (wr_select_expanded(i) = '1') then
reg_value_r(i) <= data_in(i);
......@@ -175,11 +180,11 @@ begin
-- Autoclear register (no DFF - combinatorial only). When access
-- is made, put data to output, reset value otherwise.
--------------------------------------------------------------------
reg_autoclear_gen : if (bit_in_mask(auto_clear, i) = '1') generate
reg_autoclear_gen : if (auto_clear_i(i) = '1') generate
reg_value_r(i) <= data_in(i) when wr_select_expanded(i) = '1'
else
bit_in_mask(reset_value, i);
reset_value_i(i);
end generate reg_autoclear_gen;
......@@ -189,8 +194,8 @@ begin
-----------------------------------------------------------------------
-- Registers which are not present are stuck at reset value
-----------------------------------------------------------------------
reg_not_present_gen : if (bit_in_mask(data_mask, i) = '0') generate
reg_value_r(i) <= bit_in_mask(reset_value, i);
reg_not_present_gen : if (data_mask_i(i) = '0') generate
reg_value_r(i) <= reset_value_i(i);
end generate reg_not_present_gen;
end generate bit_gen;
......
......@@ -280,6 +280,8 @@ architecture rtl of memory_registers is
constant C_NOT_RESET_POLARITY : std_logic := not G_RESET_POLARITY;
signal ewl_padded : std_logic_vector(8 downto 0);
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
......@@ -389,7 +391,7 @@ begin
DATA_WIDTH => 32,
ADDRESS_WIDTH => 16,
REGISTERED_READ => true,
CLEAR_READ_DATA => true,
CLEAR_READ_DATA => false,
RESET_POLARITY => G_RESET_POLARITY,
SUP_FILT_A => G_SUP_FILTA,
SUP_RANGE => G_SUP_RANGE,
......@@ -480,12 +482,14 @@ begin
'1' when (is_idle = '1') else
'0';
ewl_padded <= '0' & control_registers_out.ewl(7 downto 0);
status_comb(EWL_IND) <=
'1' when to_integer(unsigned(control_registers_out.ewl)) <=
to_integer(unsigned(stat_bus(STAT_TX_COUNTER_HIGH downto STAT_TX_COUNTER_LOW)))
'1' when unsigned(ewl_padded) <=
unsigned(stat_bus(STAT_TX_COUNTER_HIGH downto STAT_TX_COUNTER_LOW))
else
'1' when to_integer(unsigned(control_registers_out.ewl)) <=
to_integer(unsigned(stat_bus(STAT_RX_COUNTER_HIGH downto STAT_RX_COUNTER_LOW)))
'1' when unsigned(ewl_padded) <=
unsigned(stat_bus(STAT_RX_COUNTER_HIGH downto STAT_RX_COUNTER_LOW))
else
'0';
......
......@@ -174,7 +174,7 @@ begin
if (res_n = G_RESET_POLARITY) then
tq_counter_q <= (OTHERS => '0');
elsif (rising_edge(clk_sys)) then
if (tq_counter_allow = '1') then
if (tq_counter_ce = '1') then
tq_counter_q <= tq_counter_d;
end if;
end if;
......
......@@ -86,9 +86,6 @@ entity bit_time_fsm is
-----------------------------------------------------------------------
-- Segment end (either due to re-sync, or reaching expected length)
segm_end : in std_logic;
-- Hard synchronisation is valid
h_sync_valid : in std_logic;
-- CTU CAN FD is enabled
drv_ena : in std_logic;
......@@ -127,7 +124,7 @@ begin
----------------------------------------------------------------------------
-- Next state process (combinational)
----------------------------------------------------------------------------
next_state_proc : process(current_state, h_sync_valid, segm_end, drv_ena)
next_state_proc : process(current_state, segm_end, drv_ena)
begin
next_state <= current_state;
......
......@@ -444,7 +444,6 @@ begin
clk_sys => clk_sys, -- IN
res_n => res_n, -- IN
segm_end => segment_end, -- IN
h_sync_valid => h_sync_valid, -- IN
drv_ena => drv_ena, -- IN
is_tseg1 => is_tseg1, -- OUT
is_tseg2 => is_tseg2, -- OUT
......@@ -466,8 +465,7 @@ begin
res_n => res_n, -- IN
rx_trig_req => rx_trig_req, -- IN
tx_trig_req => tx_trig_req, -- IN
sp_control => sp_control, -- IN
rx_triggers => rx_triggers, -- OUT
tx_trigger => tx_trigger -- OUT
);
......
......@@ -120,9 +120,6 @@ entity trigger_generator is
-- TX Trigger request (Sync)
tx_trig_req : in std_logic;
-- Sample control (Nominal, Data, Secondary)
sp_control : in std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- Trigger outputs
-----------------------------------------------------------------------
......
......@@ -436,7 +436,6 @@ begin
store_data_f => store_data_f, -- IN
rec_valid_f => rec_valid_f, -- IN
rec_abort_f => rec_abort_f, -- IN
sof_pulse => sof_pulse, -- IN
write_raw_intent => write_raw_intent, -- OUT
write_ts => write_ts, -- OUT
......@@ -466,7 +465,6 @@ begin
store_ts_wr_ptr => store_ts_wr_ptr, -- IN
inc_ts_wr_ptr => inc_ts_wr_ptr, -- IN
read_increment => read_increment, -- IN
drv_bus => drv_bus, -- IN
read_pointer => read_pointer, -- OUT
read_pointer_inc_1 => read_pointer_inc_1, -- OUT
......@@ -989,6 +987,16 @@ begin
-- psl rx_buf_store_64_byte_frame_cov :
-- cover {rec_dlc = "1111" and rec_is_rtr = '0' and commit_rx_frame = '1'};
---------------------------------------------------------------------------
-- "reset_overrun_flag = '1'" only in "s_rxb_idle" state. Therefore we can
-- use this signal to check that FSM is in s_rxb_idle state!
---------------------------------------------------------------------------
-- psl sof_pulse_asrt_asrt : assert never
-- (sof_pulse = '1' and reset_overrun_flag = '0')
-- report "RX Buffer: SOF pulse should come when RX Buffer is idle!"
-- severity error;
-- <RELEASE_ON>
end architecture;
\ No newline at end of file
......@@ -94,9 +94,6 @@ entity rx_buffer_fsm is
-- Abort storing of RX Frame to RX Buffer.
rec_abort_f :in std_logic;
-- Start of Frame pulse
sof_pulse :in std_logic;
-----------------------------------------------------------------------
-- FSM outputs
-----------------------------------------------------------------------
......@@ -321,11 +318,6 @@ begin
-- report "RX Buffer: Store data or frame commit commands did not come " &
-- "when RX Buffer is receiving data!"
-- severity error;
-- psl sof_pulse_asrt_asrt : assert never
-- (sof_pulse = '1' and (curr_state /= s_rxb_idle))
-- report "RX Buffer: SOF pulse should come when RX Buffer is idle!"
-- severity error;
-- psl rx_buf_cmds_one_hot_asrt : assert always
-- (now > 0 ps) -> (cmd_join = "0000" or cmd_join = "0001" or
......
......@@ -118,12 +118,6 @@ entity rx_buffer_pointers is
-- RX Buffer RAM is being read by SW
read_increment :in std_logic;
-----------------------------------------------------------------------
-- Memory registers interface
-----------------------------------------------------------------------
-- Driving bus
drv_bus :in std_logic_vector(1023 downto 0);
-----------------------------------------------------------------------
-- Status outputs
-----------------------------------------------------------------------
......
......@@ -130,7 +130,6 @@ begin
G_DEPTH => G_RX_BUFF_SIZE,
G_ADDRESS_WIDTH => port_a_address'length,
G_RESET_POLARITY => G_RESET_POLARITY,
G_SIMULATION_RESET => false,
G_SYNC_READ => true
)
port map(
......
......@@ -143,9 +143,6 @@ entity tx_arbitrator is
-----------------------------------------------------------------------
-- Memory registers interface
-----------------------------------------------------------------------
-- Driving Bus
drv_bus :in std_logic_vector(1023 downto 0);
-- Priorities of TXT Buffers
txtb_prorities :in t_txt_bufs_priorities;
...