Commit 860c6de1 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Replaced frame related constants with generated values from IP XACT.

Separate package created. Original constants erased from CAN Constants
parent 85bde394
......@@ -223,7 +223,7 @@ resolution = 1fs
UserTimeUnit = default
; Default run length
RunLength = 0 ps
RunLength = 0 fs
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
......@@ -431,7 +431,7 @@ Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v
Project_File_7 = ../test/set_env.tcl
Project_File_P_7 = folder test_framework last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1
Project_File_8 = ../test/sanity/sanity_test.vhd
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder sanity last_compile 1516295575 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 39 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder sanity last_compile 1516300200 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 39 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_9 = ../src/Buffers_Message_Handling/messageFilter.vhd
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder Buffers_Message_Handling last_compile 1514240783 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_10 = ../src/CAN_Core/bitDeStuffing.vhd
......@@ -485,7 +485,7 @@ Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
Project_File_34 = ../test/unit/TX_Arbitrator/txar_unit.tcl
Project_File_P_34 = compile_order -1 last_compile 0 folder TX_Arbitrator dont_compile 1 group_id 0 file_type tcl ood 1
Project_File_35 = ../src/CAN_Core/protocolControl.vhd
Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder CAN_Core last_compile 1515147309 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder CAN_Core last_compile 1516300262 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_36 = ../test/unit/Prescaler/Prescaler_tb.vhd
Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder Prescaler last_compile 1514240783 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 50 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_37 = ../test/feature/feature_config.tcl
......@@ -497,7 +497,7 @@ Project_File_P_39 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
Project_File_40 = ../test/others/prescaler_v3_tb.vhd
Project_File_P_40 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder others last_compile 1515147309 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 38 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_41 = ../src/Libraries/CANconstants.vhd
Project_File_P_41 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder Libraries last_compile 1515147309 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 57 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_P_41 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder Libraries last_compile 1516299927 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 57 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_42 = ../test/unit/Int_Manager/intm_unit.tcl
Project_File_P_42 = compile_order -1 last_compile 0 folder Int_Manager dont_compile 1 group_id 0 file_type tcl ood 1
Project_File_43 = ../test/feature/tx_arb_time_tran.vhd
......@@ -519,7 +519,7 @@ Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
Project_File_51 = ../test/unit/Bit_Stuffing/Bit_Stuffing_tb.vhd
Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder Bit_Stuffing last_compile 1514240783 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 40 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_52 = ../src/CAN_Core/core_top.vhd
Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder CAN_Core last_compile 1515147309 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder CAN_Core last_compile 1516300281 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_53 = ../src/rst_sync.vhd
Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder sources last_compile 1514240783 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 52 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_54 = ../src/Buffers_Message_Handling/txtBuffer.vhd
......
......@@ -76,6 +76,8 @@ USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
use work.CANcomponents.ALL;
use work.CAN_FD_frame_format.ALL;
use work.CAN_FD_frame_format.all;
entity core_top is
PORT(
......
......@@ -167,6 +167,7 @@ USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
use work.CAN_FD_frame_format.all;
entity protocolControl is
port(
......
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
-- Copyright (C) 2017 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisor: Jiri Novak <jnovak@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Address constants for register map: NoneBit field constants for register ma
-- p: CAN_FD_frame_format. This file is autogenerated, do NOT edit!
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
package CAN_FD_frame_format is
------------------------------------------------------------------------------
-- FRAME_FORM_W register
--
-- Frame format word with basic frame information.
------------------------------------------------------------------------------
constant DLC_L : natural := 0;
constant DLC_H : natural := 3;
constant RTR_IND : natural := 5;
constant ID_TYPE_IND : natural := 6;
constant FR_TYPE_IND : natural := 7;
constant TBF_IND : natural := 8;
constant BRS_IND : natural := 9;
constant ESI_RESVD_IND : natural := 10;
-- "RTR" field enumerated values
constant NO_RTR_FRAME : std_logic := '0';
constant RTR_FRAME : std_logic := '1';
-- "ID_TYPE" field enumerated values
constant BASE : std_logic := '0';
constant EXTENDED : std_logic := '1';
-- "FR_TYPE" field enumerated values
constant NORMAL_CAN : std_logic := '0';
constant FD_CAN : std_logic := '1';
-- "TBF" field enumerated values
constant NOT_TIME_BASED : std_logic := '0';
constant TIME_BASED : std_logic := '1';
-- "BRS" field enumerated values
constant BR_NO_SHIFT : std_logic := '0';
constant BR_SHIFT : std_logic := '1';
-- "ESI_RESVD" field enumerated values
constant ESI_ERR_ACTIVE : std_logic := '0';
constant ESI_ERR_PASIVE : std_logic := '1';
------------------------------------------------------------------------------
-- IDENTIFIER_W register
--
-- CAN Identifier
------------------------------------------------------------------------------
constant IDENTIFIER_BASE_L : natural := 8;
constant IDENTIFIER_BASE_H : natural := 18;
constant IDENTIFIER_EXT_L : natural := 20;
constant IDENTIFIER_EXT_H : natural := 37;
------------------------------------------------------------------------------
-- TIMESTAMP_L_W register
--
-- Lower 32 bits of timestamp when the frame should be transmitted or when it
-- was received.
------------------------------------------------------------------------------
constant TIME_STAMP_31_0_L : natural := 16;
constant TIME_STAMP_31_0_H : natural := 47;
------------------------------------------------------------------------------
-- TIMESTAMP_U_W register
--
-- Upper 32 bits of timestamp when the frame should be transmitted or when it
-- was received.
------------------------------------------------------------------------------
constant TIMESTAMP_L_W_L : natural := 24;
constant TIMESTAMP_L_W_H : natural := 55;
------------------------------------------------------------------------------
-- DATA_1_4_W register
--
------------------------------------------------------------------------------
constant DATA_1_TO_DATA_4_L : natural := 0;
constant DATA_1_TO_DATA_4_H : natural := 31;
------------------------------------------------------------------------------
-- DATA_17_20_W register
--
------------------------------------------------------------------------------
constant DATA_17_TO_DATA_20_L : natural := 0;
constant DATA_17_TO_DATA_20_H : natural := 31;
------------------------------------------------------------------------------
-- DATA_21_24_W register
--
------------------------------------------------------------------------------
constant DATA_21_TO_DATA_24_L : natural := 8;
constant DATA_21_TO_DATA_24_H : natural := 39;
------------------------------------------------------------------------------
-- DATA_9_12_W register
--
------------------------------------------------------------------------------
constant DATA_9_TO_DATA_12_L : natural := 16;
constant DATA_9_TO_DATA_12_H : natural := 47;
------------------------------------------------------------------------------
-- DATA_49_52_W register
--
------------------------------------------------------------------------------
constant DATA_49_TO_DATA_52_L : natural := 0;
constant DATA_49_TO_DATA_52_H : natural := 31;
------------------------------------------------------------------------------
-- DATA_37_40_W register
--
------------------------------------------------------------------------------
constant DATA_37_TO_DATA_40_L : natural := 8;
constant DATA_37_TO_DATA_40_H : natural := 39;
------------------------------------------------------------------------------
-- DATA_25_28_W register
--
------------------------------------------------------------------------------
constant DATA_25_TO_DATA_28_L : natural := 16;
constant DATA_25_TO_DATA_28_H : natural := 47;
------------------------------------------------------------------------------
-- DATA_61_64_W register
--
------------------------------------------------------------------------------
constant DATA_61_TO_DATA_64_L : natural := 24;
constant DATA_61_TO_DATA_64_H : natural := 55;
------------------------------------------------------------------------------
-- DATA_41_44_W register
--
------------------------------------------------------------------------------
constant DATA_41_TO_DATA_44_L : natural := 16;
constant DATA_41_TO_DATA_44_H : natural := 47;
------------------------------------------------------------------------------
-- DATA_29_32_W register
--
------------------------------------------------------------------------------
constant DATA_29_TO_DATA_32_L : natural := 24;
constant DATA_29_TO_DATA_32_H : natural := 55;
------------------------------------------------------------------------------
-- DATA_13_16_W register
--
------------------------------------------------------------------------------
constant DATA_13_TO_DATA_16_L : natural := 24;
constant DATA_13_TO_DATA_16_H : natural := 55;
------------------------------------------------------------------------------
-- DATA_5_8_W register
--
------------------------------------------------------------------------------
constant DATA_5_TO_DATA_8_L : natural := 8;
constant DATA_5_TO_DATA_8_H : natural := 39;
------------------------------------------------------------------------------
-- DATA_57_60_W register
--
------------------------------------------------------------------------------
constant DATA_57_TO_DATA_60_L : natural := 16;
constant DATA_57_TO_DATA_60_H : natural := 47;
------------------------------------------------------------------------------
-- DATA_45_48_W register
--
------------------------------------------------------------------------------
constant DATA_45_TO_DATA_48_L : natural := 24;
constant DATA_45_TO_DATA_48_H : natural := 55;
------------------------------------------------------------------------------
-- DATA_53_56_W register
--
------------------------------------------------------------------------------
constant DATA_53_TO_DATA_56_L : natural := 8;
constant DATA_53_TO_DATA_56_H : natural := 39;
------------------------------------------------------------------------------
-- DATA_33_36_W register
--
------------------------------------------------------------------------------
constant DATA_33_TO_DATA_36_L : natural := 0;
constant DATA_33_TO_DATA_36_H : natural := 31;
end package;
\ No newline at end of file
......@@ -73,11 +73,6 @@ package CANconstants is
constant CAN_BASE_ID_LENGTH : natural := 11;
constant CAN_EXT_ID_LENGTH : natural := 18; --Length Identifier extension only
constant BASE : std_logic := '0';
constant EXTENDED : std_logic := '1';
constant NORMAL_CAN : std_logic := '0';
constant FD_CAN : std_logic := '1';
constant NO_SYNC : std_logic_vector := "00";
constant HARD_SYNC : std_logic_vector := "01";
constant RE_SYNC : std_logic_vector := "10";
......
......@@ -62,6 +62,7 @@ USE ieee.math_real.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANcomponents.ALL;
use work.CANconstants.all;
use work.CAN_FD_frame_format.all;
entity core_top_tb1 is
end entity;
......
......@@ -61,6 +61,7 @@ USE work.CANtestLib.All;
USE work.randomLib.All;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
architecture sanity_test of CAN_test is
......
......@@ -110,6 +110,7 @@ use work.CANcomponents.ALL;
USE work.CANtestLib.All;
USE work.randomLib.All;
use work.ID_transfer.all;
use work.CAN_FD_frame_format.all;
architecture Protocol_Control_unit_test of CAN_test is
......
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