Commit 851f4c33 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Separated RX Buffer FSM and RX Buffer pointers to stand-alone

modules.
parent 48b1a8b7
This diff is collapsed.
This diff is collapsed.
......@@ -476,7 +476,7 @@ architecture rtl of CAN_top_level is
-- Defining explicit architectures for used entites
----------------------------------------------------------------------------
for reg_comp : canfd_registers use entity work.canfd_registers(rtl);
for rx_buf_comp : rxBuffer use entity work.rxBuffer(rtl);
for rx_buf_comp : rx_buffer use entity work.rx_buffer(rtl);
for tx_arb_comp : txArbitrator use entity work.txArbitrator(rtl);
for mes_filt_comp : messageFilter use entity work.messageFilter(rtl);
for int_man_comp : intManager use entity work.intManager(rtl);
......@@ -559,7 +559,7 @@ begin
);
rx_buf_comp : rxBuffer
rx_buf_comp : rx_buffer
generic map(
buff_size => rx_buffer_size
)
......
......@@ -244,7 +244,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- RX Buffer module
----------------------------------------------------------------------------
component rxBuffer is
component rx_buffer is
generic(
buff_size : natural range 32 to 4096 := 32
);
......@@ -279,6 +279,58 @@ package CANcomponents is
end component;
----------------------------------------------------------------------------
-- RX Buffer FSM
----------------------------------------------------------------------------
component rx_buffer_fsm is
port(
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async. reset
signal store_metadata :in std_logic;
signal store_data :in std_logic;
signal rec_message_valid :in std_logic;
signal rec_abort :in std_logic;
signal sof_pulse :in std_logic;
signal drv_bus :in std_logic_vector(1023 downto 0);
signal write_raw_intent :out std_logic;
signal write_extra_ts :out std_logic;
signal store_extra_ts_end :out std_logic;
signal data_selector :out std_logic_vector(6 downto 0);
signal store_extra_wr_ptr :out std_logic;
signal inc_extra_wr_ptr :out std_logic;
signal reset_overrun_flag :out std_logic
);
end component;
----------------------------------------------------------------------------
-- RX Buffer Pointers
----------------------------------------------------------------------------
component rx_buffer_pointers is
generic(
buff_size : natural range 32 to 4096 := 32
);
port(
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async. reset
signal rec_abort :in std_logic;
signal commit_rx_frame :in std_logic;
signal write_raw_OK :in std_logic;
signal commit_overrun_abort :in std_logic;
signal store_extra_wr_ptr :in std_logic;
signal inc_extra_wr_ptr :in std_logic;
signal read_increment :in std_logic;
signal drv_bus :in std_logic_vector(1023 downto 0);
signal read_pointer :out natural range 0 to buff_size - 1;
signal read_pointer_inc_1 :out natural range 0 to buff_size - 1;
signal write_pointer :out natural range 0 to buff_size - 1;
signal write_pointer_raw :out natural range 0 to buff_size - 1;
signal write_pointer_extra_ts :out natural range 0 to buff_size - 1;
signal rx_mem_free_int :out natural range 0 to buff_size
);
end component;
----------------------------------------------------------------------------
-- Inferred RAM wrapper
----------------------------------------------------------------------------
......
......@@ -512,14 +512,14 @@ architecture rx_buf_unit_test of CAN_test is
end loop;
end procedure;
for rx_Buffer_comp : rxBuffer use entity work.rxBuffer(rtl);
for rx_Buffer_comp : rx_buffer use entity work.rx_buffer(rtl);
begin
----------------------------------------------------------------------------
-- Buffer component
----------------------------------------------------------------------------
rx_Buffer_comp : rxBuffer
rx_Buffer_comp : rx_buffer
generic map(
buff_size => buff_size
)
......
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