Commit 83ba10c4 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added non-reset of output register from memory word of inferred RAM.

Synthesis was adding AND gates on each line after BRAM. This is not
desirable, direct output from memory must be taken!
parent bc448cae
......@@ -151,8 +151,13 @@ begin
ram_read_process : process(res_n, clk_sys)
if (res_n = reset_polarity) then
data_out <= (OTHERS => '0');
-- pragma translate_off
if (simulation_reset) then
data_out <= (OTHERS => '0');
end if;
-- pragma translate_on
elsif (rising_edge(clk_sys)) then
data_out <= int_read_data;
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