Commit 81c59133 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge remote-tracking branch 'origin/master' into 202-txt-buffer-hazard-test

# Conflicts:
#	test/tests_debug.yml
parents a8fc51b4 6f0a5462
......@@ -7,3 +7,9 @@
*~
.fuse_hidden*
.mypy_cache
debian/ctucanfd-drv
debian/*.log
debian/*.substvars
debian/debhelper-build-stamp
debian/*.debhelper
debian/files
ctucanfd-drv (1.0.0) unstable; urgency=medium
* Initial dkms build.
-- Pavel Pisa <ppisa@pikron.com> Fri, 18 Jan 2019 19:09:04 +0100
Source: ctucanfd-drv
Maintainer: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Section: admin
Priority: optional
Build-Depends: debhelper (>=9),
dkms
Standards-Version: 1.0.0
Vcs-Browser: https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
Vcs-Git: https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core.git
Homepage: https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
Package: ctucanfd-drv
Architecture: all
Depends: ${misc:Depends}
Description: CTU CAN FD IP Core driver
CAN with Flexible Data-rate IP Core developed
at Department of Measurement of FEE CTU.
.
This package provides driver for the core.
It supports PCI express cards as well as it provides
platform driver for SoC integration when appropriate
device tree is provided.
Format: http://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
Upstream-Name: ctucanfd_ip_core
Source: https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
Files: /driver/*
Copyright: 2018-2019 Ondrej Ille <ondrej.ille@gmail.com>
2018-2019 Martin Jerabek <martin.jerabek01@gmail.com>
2018-2019 Pavel Pisa <pisa@cmp.felk.cvut.cz>
License: GPL-2.0+
Files: /src/*
Copyright: 2018-2019 Ondrej Ille <ondrej.ille@gmail.com>
2018-2019 Martin Jerabek <martin.jerabek01@gmail.com>
License: CTUCANFD-Core License
License: CTUCANFD-Core License
CTU CAN FD IP Core
Copyright (C) 2015-2018
.
Authors:
Ondrej Ille <ondrej.ille@gmail.com>
Martin Jerabek <martin.jerabek01@gmail.com>
.
Project advisors:
Jiri Novak <jnovak@fel.cvut.cz>
Pavel Pisa <pisa@cmp.felk.cvut.cz>
.
Department of Measurement (http://meas.fel.cvut.cz/)
Faculty of Electrical Engineering (http://www.fel.cvut.cz)
Czech Technical University (http://www.cvut.cz/)
.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this VHDL component and associated documentation files (the "Component"),
to deal in the Component without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Component, and to permit persons to whom the
Component is furnished to do so, subject to the following conditions:
.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Component.
.
THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
IN THE COMPONENT.
.
The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
Anybody who wants to implement this IP core on silicon has to obtain a CAN
protocol license from Bosch.
License: GPL-2.0+
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
.
On Debian systems, the complete text of the GNU General Public License
Version 2 can be found in `/usr/share/common-licenses/GPL-2'.
#!/bin/sh
for fname in ctu_can_fd.c ctu_can_fd_frame.h ctu_can_fd_hw.c ctu_can_fd_hw.h \
ctu_can_fd_regs.h ; do
echo driver/${fname} /usr/src/${PACKAGE_NAME}-${PACKAGE_VERSION}
done
for fname in Kbuild Makefile ; do
echo driver/linux/${fname} /usr/src/${PACKAGE_NAME}-${PACKAGE_VERSION}
done
driver/dkms.conf
README.md
#!/usr/bin/make -f
export DH_VERBOSE = 1
export OMIT_KERNEL_PASSES = y
PACKAGE_NAME=$(shell grep PACKAGE_NAME= driver/dkms.conf | cut -d= -f2 | cut -d\" -f2)
PACKAGE_VERSION=$(shell grep PACKAGE_VERSION= driver/dkms.conf | cut -d= -f2 | cut -d\" -f2)
export PACKAGE_NAME PACKAGE_VERSION
%:
dh $@ --with dkms
# Nothing to configure, build or auto-install (this all happens after
# installation using dkms)
override_dh_auto_configure:
override_dh_auto_build:
override_dh_auto_install:
......@@ -4930,8 +4930,8 @@ ILBP Internal loop-back option (recommended only for testing). If internal loop
\end_layout
\begin_layout Description
ENA Enable bit for the whole CAN FD Controller. When disabled, IP Core acts as if not connected to the CAN Bus.\begin_inset Newline newline\end_inset
0b0 - DISABLED - The CAN Core is disabled.\begin_inset Newline newline\end_inset
0b1 - ENABLED - The CAN Core is enabled.
0b0 - CTU_CAN_DISABLED - The CAN Core is disabled.\begin_inset Newline newline\end_inset
0b1 - CTU_CAN_ENABLED - The CAN Core is enabled.
\end_layout
\begin_layout Description
NISOFD Selection between two possible CAN FD specifications. This bit should be modified only when SETTINGS[ENA]=0.\begin_inset Newline newline\end_inset
......
......@@ -142,7 +142,7 @@ void ctu_can_fd_enable(struct ctucanfd_priv *priv, bool enable)
union ctu_can_fd_mode_command_status_settings reg;
reg.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
reg.s.ena = enable ? ENABLED : DISABLED;
reg.s.ena = enable ? CTU_CAN_ENABLED : CTU_CAN_DISABLED;
priv->write_reg(priv, CTU_CAN_FD_MODE, reg.u32);
}
......@@ -774,4 +774,21 @@ bool ctu_can_fd_insert_frame(struct ctucanfd_priv *priv,
return true;
}
u64 ctu_can_fd_read_timestamp(struct ctucanfd_priv *priv)
{
union ctu_can_fd_timestamp_low ts_low;
union ctu_can_fd_timestamp_high ts_high;
union ctu_can_fd_timestamp_high ts_high_2;
ts_high.u32 = priv->read_reg(priv, CTU_CAN_FD_TIMESTAMP_HIGH);
ts_low.u32 = priv->read_reg(priv, CTU_CAN_FD_TIMESTAMP_LOW);
ts_high_2.u32 = priv->read_reg(priv, CTU_CAN_FD_TIMESTAMP_HIGH);
if (ts_high.u32 != ts_high_2.u32){
ts_low.u32 = priv->read_reg(priv, CTU_CAN_FD_TIMESTAMP_LOW);
}
return (( (u64) ts_high_2.u32) << 32) | ( (u64) ts_low.u32);
}
// TODO: AL_CAPTURE and ERROR_CAPTURE
......@@ -316,7 +316,7 @@ static inline bool ctu_can_fd_is_enabled(struct ctucanfd_priv *priv)
union ctu_can_fd_mode_command_status_settings reg;
reg.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
return reg.s.ena == ENABLED;
return reg.s.ena == CTU_CAN_ENABLED;
}
......@@ -955,6 +955,20 @@ static inline union ctu_can_fd_debug_register
return reg;
}
/*
* Read timestamp value which is used internally by CTU CAN FD Core.
* Reads timestamp twice and checks consistency betwen upper and
* lower timestamp word.
*
* Arguments:
* priv Private info
* Returns:
* Value of timestamp in CTU CAN FD Core
*/
u64 ctu_can_fd_read_timestamp(struct ctucanfd_priv *priv);
extern const struct can_bittiming_const ctu_can_fd_bit_timing_max;
extern const struct can_bittiming_const ctu_can_fd_bit_timing_data_max;
......
......@@ -250,8 +250,8 @@ enum ctu_can_fd_settings_ilbp {
};
enum ctu_can_fd_settings_ena {
DISABLED = 0x0,
ENABLED = 0x1,
CTU_CAN_DISABLED = 0x0,
CTU_CAN_ENABLED = 0x1,
};
enum ctu_can_fd_settings_nisofd {
......
......@@ -251,7 +251,9 @@ int main(int argc, char *argv[])
case 'p':
addrs[0] = pci_find_bar(0x1172, 0xcafd, 0, 1);
if (!addrs[0])
err(1, "-p PCI device not found");
addrs[0] = pci_find_bar(0x1760, 0xff00, 0, 1);
if (!addrs[0])
err(1, "-p PCI device not found");
addrs[1] = addrs[0] + 0x4000;
break;
case 'h':
......
PACKAGE_VERSION="1.0.0"
PACKAGE_NAME="ctucanfd-drv"
CLEAN="make clean"
BUILT_MODULE_NAME[0]="ctucanfd"
BUILT_MODULE_LOCATION[0]=""
DEST_MODULE_LOCATION[0]="/extra"
MAKE[0]="make KERNEL_VERSION=$kernelver -C ${dkms_tree}/${PACKAGE_NAME}/${PACKAGE_VERSION}/build"
AUTOINSTALL="yes"
CROSS_COMPILE= arm-linux-gnueabihf-
ifeq ($(KERNEL_VERSION),)
CROSS_COMPILE?= arm-linux-gnueabihf-
KDIR ?= /home/mjerabek/projects/kernel/linux-4.15-build/zynq
ARCH=arm
ifeq ($(shell hostname),hathi)
INSTALL_DIR=/srv/nfs4/debian-armhf-devel
endif
#KDIR ?= /lib/modules/$(shell uname -r)/build
#ARCH ?= x86_64
else
KDIR = /lib/modules/$(KERNEL_VERSION)/build
endif
MAKEARGS := -C $(KDIR)
MAKEARGS += $(if $(ARCH),ARCH=$(ARCH))
MAKEARGS += $(if $(CROSS_COMPILE),CROSS_COMPILE=$(CROSS_COMPILE))
$(warning "$(MAKEARGS)")
default:
$(MAKE) -C $(KDIR) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) M=$$PWD
ifeq ($(shell hostname),hathi)
-rm -f /srv/nfs4/debian-armhf-devel/ctucanfd.ko
cp ctucanfd.ko /srv/nfs4/debian-armhf-devel/
$(MAKE) $(MAKEARGS) M=$$PWD
ifneq ($(INSTALL_DIR),)
-rm -f $(INSTALL_DIR)/ctucanfd.ko
cp ctucanfd.ko $(INSTALL_DIR)/
endif
clean:
$(MAKE) -C $(KDIR) M=$$PWD ARCH=arm clean
$(MAKE) $(MAKEARGS) M=$$PWD clean
This diff is collapsed.
#!/usr/bin/python3
"""
Generate vivado component file in /src/component.xml.
Serves to update the list of source files -- run when you add/delete/rename
a src vhdl file.
"""
from jinja2 import Environment, FileSystemLoader, select_autoescape
from pathlib import Path
d = Path(__file__).parent
jinja_env = Environment(
loader=FileSystemLoader(str(d)),
autoescape=select_autoescape(['html', 'xml']))
template = jinja_env.get_template('component.xml.j2')
src_dir = d / '..' / 'src'
files = [str(f.relative_to(src_dir)) for f in src_dir.glob('**/*.vhd')]
files = sorted(files)
contents = template.render(files=files)
with (src_dir / 'component.xml').open('wt', encoding='utf-8') as f:
f.write(contents)
......@@ -532,14 +532,14 @@
<ipxact:bitWidth>1</ipxact:bitWidth>
<ipxact:enumeratedValues>
<ipxact:enumeratedValue>
<ipxact:name>ENABLED</ipxact:name>
<ipxact:displayName>ENABLED</ipxact:displayName>
<ipxact:name>CTU_CAN_ENABLED</ipxact:name>
<ipxact:displayName>CTU_CAN_ENABLED</ipxact:displayName>
<ipxact:description>The CAN Core is enabled.</ipxact:description>
<ipxact:value>1</ipxact:value>
</ipxact:enumeratedValue>
<ipxact:enumeratedValue>
<ipxact:name>DISABLED</ipxact:name>
<ipxact:displayName>DISABLED</ipxact:displayName>
<ipxact:name>CTU_CAN_DISABLED</ipxact:name>
<ipxact:displayName>CTU_CAN_DISABLED</ipxact:displayName>
<ipxact:description>The CAN Core is disabled.</ipxact:description>
<ipxact:value>0</ipxact:value>
</ipxact:enumeratedValue>
......
......@@ -86,6 +86,9 @@
-- reading wrong value from TRV_DELAY register during measurment.
-- 10.12.2018 Re-factored, added generic Shift register instances. Added
-- generic synchronisation chain module.
-- 16.1.2019 Replaced TX Data Shift register with FIFO like TX Data Cache.
-- TX Data are stored only once per bit. TX Data Cache consumes
-- drastically less DFFs.
--------------------------------------------------------------------------------
Library ieee;
......@@ -203,17 +206,15 @@ architecture rtl of bus_sampling is
-- Shift registers length
constant SSP_SHIFT_LENGTH : natural := 130;
constant TX_DATA_SHIFT_LENGTH : natural := 130;
-- Depth of FIFO Cache for TX Data
constant TX_CACHE_DEPTH : natural := 8;
-- Reset value for secondar sampling point shift registers
constant SSP_SHIFT_RST_VAL : std_logic_vector(SSP_SHIFT_LENGTH - 1
downto 0) :=
(OTHERS => '0');
constant TX_DATA_SHIFT_RST_VAL : std_logic_vector(TX_DATA_SHIFT_LENGTH - 1
downto 0) :=
(OTHERS => RECESSIVE);
constant SSP_DELAY_SAT_VAL : natural := SSP_SHIFT_LENGTH - 1;
-----------------------------------------------------------------------------
......@@ -263,10 +264,6 @@ architecture rtl of bus_sampling is
signal sample_sec_del_1 : std_logic;
signal sample_sec_del_2 : std_logic;
-- Shift Register for storing the TX data for secondary sample point
signal tx_data_shift : std_logic_vector
(TX_DATA_SHIFT_LENGTH - 1 downto 0);
-- Delayed TX Data from TX Data shift register at position of secondary
-- sampling point.
signal tx_data_delayed : std_logic;
......@@ -444,41 +441,33 @@ begin
output => open
);
----------------------------------------------------------------------------
-- Shift register for TX data. Stored by shift register to be compared
-- with sampled RX Data in Secondary sampling point to detect bit error.
----------------------------------------------------------------------------
tx_data_shift_reg_comp : shift_reg
generic map(
reset_polarity => ACT_RESET,
reset_value => TX_DATA_SHIFT_RST_VAL,
width => TX_DATA_SHIFT_LENGTH,
shift_down => false
)
port map(
clk => clk_sys,
res_n => shift_regs_res_n,
input => data_tx,
enable => '1',
reg_stat => tx_data_shift,
output => open
);
----------------------------------------------------------------------------
-- Secondary sampling point address decoder. Secondary sampling point
-- is taken from SSP Shift register at position of transceiver delay.
----------------------------------------------------------------------------
sample_sec_comb <= sample_sec_shift(to_integer(unsigned(ssp_delay)));
----------------------------------------------------------------------------
-- Delayed TX data address decoder. At the time of secondary sampling point,
-- TX data from TX Data shift register at position of transceiver delay are
-- taken for bit error detection!
-- TX DATA Cache. Stores TX Data when Sample point enters the SSP shift
-- register and reads data when Sample point steps out of shift register.
-- This gets the TX data which correspond to the RX Bit in Secondary
-- sampling point.
----------------------------------------------------------------------------
tx_data_delayed <= tx_data_shift(to_integer(unsigned(ssp_delay)));
tx_data_cache_comp : tx_data_cache
generic map(
reset_polarity => ACT_RESET,
tx_cache_depth => TX_CACHE_DEPTH,
tx_cache_res_val => RECESSIVE
)
port map(
clk_sys => clk_sys,
res_n => shift_regs_res_n,
write => sample_dbt,
read => sample_sec,
data_in => data_tx,
data_out => tx_data_delayed
);
----------------------------------------------------------------------------
......@@ -559,7 +548,7 @@ begin
elsif rising_edge(clk_sys) then
if (drv_ena = ENABLED) then
if (drv_ena = CTU_CAN_ENABLED) then
case sp_control is
----------------------------------------------------------------
......@@ -610,7 +599,7 @@ begin
elsif rising_edge(clk_sys) then
if (drv_ena = ENABLED and bit_err_enable = '1') then
if (drv_ena = CTU_CAN_ENABLED and bit_err_enable = '1') then
case sp_control is
----------------------------------------------------------------
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- TX Data Cache (FIFO-like). Stores TX Data into FIFO buffer. TX Data are
-- stored in time of regular sample point and read at the time of delayed
-- sample point. Read data are used for bit error detection.
--------------------------------------------------------------------------------
-- 16.01.2019 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
use work.can_constants.all;
use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
entity tx_data_cache is
generic(
-- Reset polarity
constant reset_polarity : std_logic;
-- Depth of FIFO (Number of bits that can be stored)
constant tx_cache_depth : natural range 4 to 32 := 8;
-- FIFO reset value
constant tx_cache_res_val : std_logic
);
port(
------------------------------------------------------------------------
-- Clock and Async reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- Store input data
signal write :in std_logic;
-- Read output data
signal read :in std_logic;
------------------------------------------------------------------------
-- Data signals
------------------------------------------------------------------------
signal data_in :in std_logic;
signal data_out :out std_logic
);
end entity;
architecture rtl of tx_data_cache is
-- Cache Memory (FIFO in DFFs)
signal tx_cache_mem : std_logic_vector(tx_cache_depth - 1 downto 0);
---------------------------------------------------------------------------
-- Access pointers
---------------------------------------------------------------------------
-- Write Pointer
signal write_pointer : natural range 0 to tx_cache_depth - 1;
signal write_pointer_nxt : natural range 0 to tx_cache_depth - 1;
-- Read pointer
signal read_pointer : natural range 0 to tx_cache_depth - 1;
signal read_pointer_nxt : natural range 0 to tx_cache_depth - 1;
begin
----------------------------------------------------------------------------
-- Combinationally incrementing write and read pointers
----------------------------------------------------------------------------
write_pointer_nxt <= (write_pointer + 1) mod tx_cache_depth;
read_pointer_nxt <= (read_pointer + 1) mod tx_cache_depth;
----------------------------------------------------------------------------
-- Incrementing the pointers upon read or write.
----------------------------------------------------------------------------
write_ptr_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
write_pointer <= 0;
elsif (rising_edge(clk_sys)) then
if (write = '1') then
write_pointer <= write_pointer_nxt;
end if;
end if;
end process;
read_ptr_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
read_pointer <= 0;
elsif (rising_edge(clk_sys)) then
if (read = '1') then
read_pointer <= read_pointer_nxt;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Storing data to FIFO.
----------------------------------------------------------------------------
tx_cache_mem_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
tx_cache_mem <= (OTHERS => tx_cache_res_val);
elsif (rising_edge(clk_sys)) then
if (write = '1') then