Commit 80991274 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added TX_COMMAND, TX_STATUS and TX_PRIORITY registers.

parent 0f26ebd4
This diff is collapsed.
......@@ -81,8 +81,10 @@ enum can_fd_8bit_regs {
RX_DATA = 0x50,
TRV_DELAY = 0x54,
TX_STATUS = 0x58,
TX_SETTINGS = 0x5c,
ERR_CAPT = 0x60,
TX_COMMAND = 0x5c,
TX_SETTINGS = 0x5e,
TX_PRIORITY = 0x60,
ERR_CAPT = 0x64,
RX_COUNTER = 0xac,
TX_COUNTER = 0xb0,
LOG_TRIG_CONFIG = 0xb8,
......@@ -611,49 +613,62 @@ union tx_status {
struct tx_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
/* TX_STATUS */
uint32_t txt1e : 1;
uint32_t txt1ts : 1;
uint32_t txt2e : 1;
uint32_t txt2ts : 1;
uint32_t reserved_15_4 : 12;
uint32_t txts : 1;
uint32_t reserved_31_17 : 15;
uint32_t tx1s : 4;
uint32_t tx2s : 4;
uint32_t reserved_31_8 : 24;
#else
uint32_t reserved_31_17 : 15;
uint32_t txts : 1;
uint32_t reserved_15_4 : 12;
uint32_t txt2ts : 1;
uint32_t txt2e : 1;
uint32_t txt1ts : 1;
uint32_t txt1e : 1;
uint32_t reserved_31_8 : 24;
uint32_t tx2s : 4;
uint32_t tx1s : 4;
#endif
} s;
};
union tx_settings {
union tx_command_tx_settings {
uint32_t u32;
struct tx_settings_s {
struct tx_command_tx_settings_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_1_0 : 2;
/* TX_COMMAND */
uint32_t txce : 1;
uint32_t txcr : 1;
uint32_t txca : 1;
uint32_t reserved_7_3 : 5;
uint32_t txi1 : 1;
uint32_t txi2 : 1;
uint32_t reserved_17_10 : 8;
/* TX_SETTINGS */
uint32_t bdir : 1;
uint32_t frsw : 1;
uint32_t reserved_15_4 : 12;
uint32_t txt1a : 1;
uint32_t reserved_31_20 : 12;
#else
uint32_t reserved_31_20 : 12;
uint32_t frsw : 1;
uint32_t bdir : 1;
uint32_t reserved_17_10 : 8;
uint32_t txi2 : 1;
uint32_t txi1 : 1;
uint32_t reserved_7_3 : 5;
uint32_t txca : 1;
uint32_t txcr : 1;
uint32_t txce : 1;
#endif
} s;
};
union tx_priority {
uint32_t u32;
struct tx_priority_s {
#ifdef __BIG_ENDIAN_BITFIELD
/* TX_PRIORITY */
uint32_t txt1p : 3;
uint32_t txt2a : 1;
uint32_t reserved_3 : 1;
uint32_t txt2p : 3;
uint32_t reserved_31_24 : 8;
uint32_t reserved_31_7 : 25;
#else
uint32_t reserved_31_24 : 8;
uint32_t reserved_31_7 : 25;
uint32_t txt2p : 3;
uint32_t txt2a : 1;
uint32_t reserved_3 : 1;
uint32_t txt1p : 3;
uint32_t txt1a : 1;
uint32_t reserved_15_4 : 12;
uint32_t frsw : 1;
uint32_t bdir : 1;
uint32_t reserved_1_0 : 2;
#endif
} s;
};
......
......@@ -92,8 +92,10 @@ package CAN_FD_register_map is
constant RX_DATA_ADR : std_logic_vector(11 downto 0) := x"050";
constant TRV_DELAY_ADR : std_logic_vector(11 downto 0) := x"054";
constant TX_STATUS_ADR : std_logic_vector(11 downto 0) := x"058";
constant TX_SETTINGS_ADR : std_logic_vector(11 downto 0) := x"05C";
constant ERR_CAPT_ADR : std_logic_vector(11 downto 0) := x"060";
constant TX_COMMAND_ADR : std_logic_vector(11 downto 0) := x"05C";
constant TX_SETTINGS_ADR : std_logic_vector(11 downto 0) := x"05E";
constant TX_PRIORITY_ADR : std_logic_vector(11 downto 0) := x"060";
constant ERR_CAPT_ADR : std_logic_vector(11 downto 0) := x"064";
constant RX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"0AC";
constant TX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"0B0";
constant LOG_TRIG_CONFIG_ADR : std_logic_vector(11 downto 0) := x"0B8";
......@@ -787,17 +789,40 @@ package CAN_FD_register_map is
--
-- Status of TXT Buffers.
------------------------------------------------------------------------------
constant TXT1E_IND : natural := 0;
constant TXT1TS_IND : natural := 1;
constant TXT2E_IND : natural := 2;
constant TXT2TS_IND : natural := 3;
constant TXTS_IND : natural := 16;
constant TX1S_L : natural := 0;
constant TX1S_H : natural := 3;
constant TX2S_L : natural := 4;
constant TX2S_H : natural := 7;
-- "TX1S" field enumerated values
constant TXT_TRAN : std_logic_vector(3 downto 0) := x"A";
constant TXT_ABTP : std_logic_vector(3 downto 0) := x"B";
constant TXT_OK : std_logic_vector(3 downto 0) := x"64";
constant TXT_ERR : std_logic_vector(3 downto 0) := x"6E";
constant TXT_ABT : std_logic_vector(3 downto 0) := x"6F";
constant TXT_EMPTY : std_logic_vector(3 downto 0) := x"3E8";
-- TX_STATUS register reset values
constant TXT2E_RSTVAL : std_logic := '1';
constant TXT1E_RSTVAL : std_logic := '1';
constant TXT1TS_RSTVAL : std_logic := '0';
constant TXT2TS_RSTVAL : std_logic := '0';
constant TX2S_RSTVAL : std_logic_vector(3 downto 0) := x"3E8";
constant TX1S_RSTVAL : std_logic_vector(3 downto 0) := x"3E8";
------------------------------------------------------------------------------
-- TX_COMMAND register
--
-- Command register for TXT Buffers. Command is activated by setting TXC(E,C,R
-- ) bit to logic 1. Buffer that receives the command is selected by setting b
-- it TXBI(1..8) to logic 1. Command and index must be set by single access. R
-- egister is automatically erased upon the command completion and 0 deos not
-- need to be written. Reffer to description of TXT Buffer circuit for TXT buf
-- fer State machine.
------------------------------------------------------------------------------
constant TXCE_IND : natural := 0;
constant TXCR_IND : natural := 1;
constant TXCA_IND : natural := 2;
constant TXI1_IND : natural := 8;
constant TXI2_IND : natural := 9;
-- TX_COMMAND register reset values
------------------------------------------------------------------------------
-- TX_SETTINGS register
......@@ -805,20 +830,26 @@ package CAN_FD_register_map is
-- This register controls the access into TX buffers. All bits are active in l
-- ogic 1.
------------------------------------------------------------------------------
constant BDIR_IND : natural := 2;
constant FRSW_IND : natural := 3;
constant TXT1A_IND : natural := 16;
constant TXT1P_L : natural := 17;
constant TXT1P_H : natural := 19;
constant TXT2A_IND : natural := 20;
constant TXT2P_L : natural := 21;
constant TXT2P_H : natural := 23;
constant BDIR_IND : natural := 18;
constant FRSW_IND : natural := 19;
-- TX_SETTINGS register reset values
constant TXT1A_RSTVAL : std_logic := '0';
constant TXT2A_RSTVAL : std_logic := '0';
constant BDIR_RSTVAL : std_logic := '0';
constant FRSW_RSTVAL : std_logic := '0';
------------------------------------------------------------------------------
-- TX_PRIORITY register
--
-- Priority of the TXT Buffers in TX Arbitrator. Higher priority value signals
-- that buffer is selected earlier for transmission. If two buffers have equa
-- l priorities, the one with lower index is selected.
------------------------------------------------------------------------------
constant TXT1P_L : natural := 0;
constant TXT1P_H : natural := 2;
constant TXT2P_L : natural := 4;
constant TXT2P_H : natural := 6;
-- TX_PRIORITY register reset values
constant TXT1P_RSTVAL : std_logic_vector(2 downto 0) := "001";
constant TXT2P_RSTVAL : std_logic_vector(2 downto 0) := "000";
......
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