Commit 7eb9997c authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Added SSP_CFG register. Implemented secondary sampling point delay.

Added saturation on SSP delay.
Separated TX,RX edge detection to stand-alone modules.
parent 5f5776d1
...@@ -2182,7 +2182,13 @@ hyperref[ERR_CAPT]{ERR\backslash textunderscore CAPT}\end_layout ...@@ -2182,7 +2182,13 @@ hyperref[ERR_CAPT]{ERR\backslash textunderscore CAPT}\end_layout
\begin_inset Text \begin_inset Text
   
\begin_layout Plain Layout \begin_layout Plain Layout
Reserved\end_layout \begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
hyperref[SSP_CFG]{SSP\backslash textunderscore CFG}\end_layout
\end_inset
\end_layout
   
\end_inset \end_inset
</cell> </cell>
...@@ -2190,7 +2196,13 @@ Reserved\end_layout ...@@ -2190,7 +2196,13 @@ Reserved\end_layout
\begin_inset Text \begin_inset Text
   
\begin_layout Plain Layout \begin_layout Plain Layout
Reserved\end_layout \begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
hyperref[SSP_CFG]{SSP\backslash textunderscore CFG}\end_layout
\end_inset
\end_layout
   
\end_inset \end_inset
</cell> </cell>
...@@ -29230,6 +29242,527 @@ TRV_DELAY_VALUE When sending CAN FD Frame with bit rate shift, transceiver delay ...@@ -29230,6 +29242,527 @@ TRV_DELAY_VALUE When sending CAN FD Frame with bit rate shift, transceiver delay
\end_inset \end_inset
\end_layout \end_layout
\begin_layout Subsection \begin_layout Subsection
SSP_CFG
\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
label{SSP_CFG
}\end_layout
\end_inset
\end_layout
\begin_layout Description
Type: read-write
\end_layout
\begin_layout Description
Address: 0x7A
\end_layout
\begin_layout Description
Size: 2 bytes
\end_layout
\begin_layout Standard
Configuration of Secondary sampling point which is used for Transmitter in Data Bit-Rate.
\end_layout
\begin_layout Standard
\noindent
\align center
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</lyxtabular>
\end_inset
\end_layout
\begin_layout Description
SSP_OFFSET Secondary sampling point offset.
\end_layout
\begin_layout Description
SSP_SRC Source of secondary sampling point delay. Measured in clock cycles, not Time quanta! Sampling point is delayed from regular sampling point by a value configured by this register.\begin_inset Newline newline\end_inset
0b00 - SSP_SRC_MEASURED - Use measured value (also available in TRV_DELAY_REGISTER).\begin_inset Newline newline\end_inset
0b01 - SSP_SRC_MEAS_N_OFFSET - Use measured value (available in TRV_DELAY) + SSP_OFFSET. If the result is higher than 128, delay of 128 will be used. \begin_inset Newline newline\end_inset
0b10 - SSP_SRC_OFFSET - Use SSP_OFFSET value.
\end_layout
\begin_layout Standard
\begin_inset VSpace bigskip
\end_inset
\end_layout
\begin_layout Subsection
RX_COUNTER RX_COUNTER
\begin_inset ERT \begin_inset ERT
status open status open
......
...@@ -80,6 +80,7 @@ enum ctu_can_fd_can_registers { ...@@ -80,6 +80,7 @@ enum ctu_can_fd_can_registers {
CTU_CAN_FD_ERR_CAPT = 0x74, CTU_CAN_FD_ERR_CAPT = 0x74,
CTU_CAN_FD_ALC = 0x75, CTU_CAN_FD_ALC = 0x75,
CTU_CAN_FD_TRV_DELAY = 0x78, CTU_CAN_FD_TRV_DELAY = 0x78,
CTU_CAN_FD_SSP_CFG = 0x7a,
CTU_CAN_FD_RX_COUNTER = 0x7c, CTU_CAN_FD_RX_COUNTER = 0x7c,
CTU_CAN_FD_TX_COUNTER = 0x80, CTU_CAN_FD_TX_COUNTER = 0x80,
CTU_CAN_FD_DEBUG_REGISTER = 0x84, CTU_CAN_FD_DEBUG_REGISTER = 0x84,
...@@ -843,20 +844,33 @@ enum ctu_can_fd_alc_alc_id_field { ...@@ -843,20 +844,33 @@ enum ctu_can_fd_alc_alc_id_field {
ALC_RTR = 0x4, ALC_RTR = 0x4,
}; };
union ctu_can_fd_trv_delay { union ctu_can_fd_trv_delay_ssp_cfg {
uint32_t u32; uint32_t u32;
struct ctu_can_fd_trv_delay_s { struct ctu_can_fd_trv_delay_ssp_cfg_s {
#ifdef __LITTLE_ENDIAN_BITFIELD #ifdef __LITTLE_ENDIAN_BITFIELD
/* TRV_DELAY */ /* TRV_DELAY */
uint32_t trv_delay_value : 16; uint32_t trv_delay_value : 16;
uint32_t reserved_31_16 : 16; /* SSP_CFG */
uint32_t ssp_offset : 7;
uint32_t reserved_23 : 1;
uint32_t ssp_src : 2;
uint32_t reserved_31_26 : 6;
#else #else
uint32_t reserved_31_16 : 16; uint32_t reserved_31_26 : 6;
uint32_t ssp_src : 2;
uint32_t reserved_23 : 1;
uint32_t ssp_offset : 7;
uint32_t trv_delay_value : 16; uint32_t trv_delay_value : 16;
#endif #endif
} s; } s;
}; };
enum ctu_can_fd_ssp_cfg_ssp_src {
SSP_SRC_MEASURED = 0x0,
SSP_SRC_MEAS_N_OFFSET = 0x1,
SSP_SRC_OFFSET = 0x2,
};
union ctu_can_fd_rx_counter { union ctu_can_fd_rx_counter {
uint32_t u32; uint32_t u32;
struct ctu_can_fd_rx_counter_s { struct ctu_can_fd_rx_counter_s {
......
...@@ -1468,6 +1468,57 @@ ...@@ -1468,6 +1468,57 @@
<ipxact:bitWidth>32</ipxact:bitWidth> <ipxact:bitWidth>32</ipxact:bitWidth>
</ipxact:field> </ipxact:field>
</ipxact:register> </ipxact:register>
<ipxact:register>
<ipxact:name>SSP_CFG</ipxact:name>
<ipxact:description>Configuration of Secondary sampling point which is used for Transmitter in Data Bit-Rate.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h7A</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>