Commit 7d847f3c authored by Martin Jeřábek's avatar Martin Jeřábek

rename tb_signal_delayer to signal_delayer

Mainly to silence VUnit warnings. It's also true that it's not a testbench,
so it should not look like one.
parent 8140fe83
......@@ -48,7 +48,7 @@
library ieee;
use ieee.std_logic_1164.all;
entity tb_signal_delayer_vec is
entity signal_delayer_vec is
generic (
NSAMPLES : positive;
DWIDTH : positive
......@@ -60,7 +60,7 @@ entity tb_signal_delayer_vec is
);
end entity;
architecture tb of tb_signal_delayer_vec is
architecture tb of signal_delayer_vec is
type data_type is array(0 to NSAMPLES-1) of time;
type dataval_type is array(0 to NSAMPLES-1) of std_logic_vector(DWIDTH-1 downto 0);
signal first : boolean := true;
......@@ -124,7 +124,7 @@ end;
library ieee;
use ieee.std_logic_1164.all;
entity tb_signal_delayer is
entity signal_delayer is
generic (
NSAMPLES : positive
);
......@@ -135,10 +135,10 @@ entity tb_signal_delayer is
);
end entity;
architecture tb of tb_signal_delayer is
architecture tb of signal_delayer is
signal input_v, delayed_v : std_logic_vector(0 downto 0);
begin
i_sdv: entity work.tb_signal_delayer_vec
i_sdv: entity work.signal_delayer_vec
generic map (
NSAMPLES => NSAMPLES,
DWIDTH => 1
......
......@@ -572,7 +572,7 @@ begin
delay_matrix(j, i) <= bus_matrix_to_delay(bus_matrix(j, i));
i_txdelay : entity work.tb_signal_delayer
i_txdelay : entity work.signal_delayer
generic map (
NSAMPLES => 16
)
......
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